diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-17 12:56:50 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-27 13:48:31 -0400 |
commit | b45a67934faeba042dbf6ebe47c520db3ef4090d (patch) | |
tree | 771f8c223a47281da915fee3348167724c332f56 /drivers/gpu/nvgpu/gk20a | |
parent | 0c45c5fcb60810f06b0ae05270f0fa7e32d31869 (diff) |
gpu: nvgpu: Use nvgpu_timeout for all loops
There were still a few remaining loops where we did not use
nvgpu_timeout and required Tegra specific functions for detecting if
timeout should be skipped. Replace all of them with nvgpu_timeout and
remove including chip-id.h where possible.
FE power mode timeout loop also used wrong delay value. It always
waited for the whole max timeout instead of looping with smaller
increments.
If SEC2 ACR boot fails to halt, we should not try to check ACR result
from mailbox. Add an early return for that case.
JIRA NVGPU-16
Change-Id: I9f0984250d7d01785755338e39822e6631dcaa5a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323227
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 |
5 files changed, 38 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 63ae1da1..b23cabe8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/delay.h> /* for udelay */ | 20 | #include <linux/delay.h> /* for udelay */ |
21 | #include <linux/mm.h> /* for totalram_pages */ | 21 | #include <linux/mm.h> /* for totalram_pages */ |
22 | #include <linux/scatterlist.h> | 22 | #include <linux/scatterlist.h> |
23 | #include <soc/tegra/chip-id.h> | ||
24 | #include <linux/debugfs.h> | 23 | #include <linux/debugfs.h> |
25 | #include <uapi/linux/nvgpu.h> | 24 | #include <uapi/linux/nvgpu.h> |
26 | #include <linux/vmalloc.h> | 25 | #include <linux/vmalloc.h> |
@@ -1587,7 +1586,6 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1587 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 1586 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
1588 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 1587 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
1589 | u32 last_method_data = 0; | 1588 | u32 last_method_data = 0; |
1590 | int retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; | ||
1591 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 1589 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
1592 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 1590 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
1593 | struct mem_desc *ctxheader = &ctx->mem; | 1591 | struct mem_desc *ctxheader = &ctx->mem; |
@@ -1603,18 +1601,21 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1603 | goto clean_up; | 1601 | goto clean_up; |
1604 | } | 1602 | } |
1605 | if (!platform->is_fmodel) { | 1603 | if (!platform->is_fmodel) { |
1604 | struct nvgpu_timeout timeout; | ||
1605 | |||
1606 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | ||
1607 | NVGPU_TIMER_CPU_TIMER); | ||
1606 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1608 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1607 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); | 1609 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); |
1608 | do { | 1610 | do { |
1609 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1611 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1610 | if (req == gr_fe_pwr_mode_req_done_v()) | 1612 | if (req == gr_fe_pwr_mode_req_done_v()) |
1611 | break; | 1613 | break; |
1612 | udelay(FE_PWR_MODE_TIMEOUT_MAX); | 1614 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); |
1613 | } while (--retries || !tegra_platform_is_silicon()); | 1615 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1616 | "timeout forcing FE on")); | ||
1614 | } | 1617 | } |
1615 | 1618 | ||
1616 | if (!retries) | ||
1617 | gk20a_err(g->dev, "timeout forcing FE on"); | ||
1618 | 1619 | ||
1619 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), | 1620 | gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), |
1620 | gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() | | 1621 | gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() | |
@@ -1643,19 +1644,20 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1643 | udelay(10); | 1644 | udelay(10); |
1644 | 1645 | ||
1645 | if (!platform->is_fmodel) { | 1646 | if (!platform->is_fmodel) { |
1647 | struct nvgpu_timeout timeout; | ||
1648 | |||
1649 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | ||
1650 | NVGPU_TIMER_CPU_TIMER); | ||
1646 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1651 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1647 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); | 1652 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); |
1648 | 1653 | ||
1649 | retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; | ||
1650 | do { | 1654 | do { |
1651 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1655 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1652 | if (req == gr_fe_pwr_mode_req_done_v()) | 1656 | if (req == gr_fe_pwr_mode_req_done_v()) |
1653 | break; | 1657 | break; |
1654 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); | 1658 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); |
1655 | } while (--retries || !tegra_platform_is_silicon()); | 1659 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1656 | 1660 | "timeout setting FE power to auto")); | |
1657 | if (!retries) | ||
1658 | gk20a_err(g->dev, "timeout setting FE power to auto"); | ||
1659 | } | 1661 | } |
1660 | 1662 | ||
1661 | /* clear scc ram */ | 1663 | /* clear scc ram */ |
@@ -4996,13 +4998,14 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4996 | 4998 | ||
4997 | static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | 4999 | static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) |
4998 | { | 5000 | { |
4999 | int retries = CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / | 5001 | struct nvgpu_timeout timeout; |
5000 | CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT; | ||
5001 | bool fecs_scrubbing; | 5002 | bool fecs_scrubbing; |
5002 | bool gpccs_scrubbing; | 5003 | bool gpccs_scrubbing; |
5003 | 5004 | ||
5004 | gk20a_dbg_fn(""); | 5005 | gk20a_dbg_fn(""); |
5005 | 5006 | ||
5007 | nvgpu_timeout_init(g, &timeout, CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / 1000, | ||
5008 | NVGPU_TIMER_CPU_TIMER); | ||
5006 | do { | 5009 | do { |
5007 | fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & | 5010 | fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & |
5008 | (gr_fecs_dmactl_imem_scrubbing_m() | | 5011 | (gr_fecs_dmactl_imem_scrubbing_m() | |
@@ -5018,7 +5021,7 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | |||
5018 | } | 5021 | } |
5019 | 5022 | ||
5020 | udelay(CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 5023 | udelay(CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
5021 | } while (--retries || !tegra_platform_is_silicon()); | 5024 | } while (!nvgpu_timeout_expired(&timeout)); |
5022 | 5025 | ||
5023 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); | 5026 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); |
5024 | return -ETIMEDOUT; | 5027 | return -ETIMEDOUT; |
@@ -8663,8 +8666,7 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8663 | 8666 | ||
8664 | usleep_range(delay, delay * 2); | 8667 | usleep_range(delay, delay * 2); |
8665 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 8668 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
8666 | } while (!nvgpu_timeout_expired(&timeout) | 8669 | } while (!nvgpu_timeout_expired(&timeout)); |
8667 | || !tegra_platform_is_silicon()); | ||
8668 | 8670 | ||
8669 | dbgr_control0 = gk20a_readl(g, | 8671 | dbgr_control0 = gk20a_readl(g, |
8670 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); | 8672 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 34a96971..9942e58f 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -17,7 +17,9 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | |||
20 | #include <trace/events/gk20a.h> | 21 | #include <trace/events/gk20a.h> |
22 | #include <nvgpu/timers.h> | ||
21 | 23 | ||
22 | #include "gk20a.h" | 24 | #include "gk20a.h" |
23 | 25 | ||
@@ -106,7 +108,6 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
106 | int err = 0; | 108 | int err = 0; |
107 | struct gr_gk20a *gr = &g->gr; | 109 | struct gr_gk20a *gr = &g->gr; |
108 | u32 fbp, slice, ctrl1, val, hw_op = 0; | 110 | u32 fbp, slice, ctrl1, val, hw_op = 0; |
109 | int retry = 200; | ||
110 | u32 slices_per_fbp = | 111 | u32 slices_per_fbp = |
111 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v( | 112 | ltc_ltcs_ltss_cbc_param_slices_per_fbp_v( |
112 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); | 113 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); |
@@ -140,6 +141,9 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
140 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); | 141 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | hw_op); |
141 | 142 | ||
142 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { | 143 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { |
144 | struct nvgpu_timeout timeout; | ||
145 | |||
146 | nvgpu_timeout_init(g, &timeout, 200, NVGPU_TIMER_RETRY_TIMER); | ||
143 | for (slice = 0; slice < slices_per_fbp; slice++) { | 147 | for (slice = 0; slice < slices_per_fbp; slice++) { |
144 | 148 | ||
145 | 149 | ||
@@ -147,18 +151,15 @@ static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
147 | fbp * ltc_stride + | 151 | fbp * ltc_stride + |
148 | slice * lts_stride; | 152 | slice * lts_stride; |
149 | 153 | ||
150 | retry = 200; | ||
151 | do { | 154 | do { |
152 | val = gk20a_readl(g, ctrl1); | 155 | val = gk20a_readl(g, ctrl1); |
153 | if (!(val & hw_op)) | 156 | if (!(val & hw_op)) |
154 | break; | 157 | break; |
155 | retry--; | ||
156 | udelay(5); | 158 | udelay(5); |
157 | 159 | ||
158 | } while (retry >= 0 || | 160 | } while (!nvgpu_timeout_expired(&timeout)); |
159 | !tegra_platform_is_silicon()); | ||
160 | 161 | ||
161 | if (retry < 0 && tegra_platform_is_silicon()) { | 162 | if (nvgpu_timeout_peek_expired(&timeout)) { |
162 | gk20a_err(dev_from_gk20a(g), | 163 | gk20a_err(dev_from_gk20a(g), |
163 | "comp tag clear timeout\n"); | 164 | "comp tag clear timeout\n"); |
164 | err = -EBUSY; | 165 | err = -EBUSY; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9e6dc74c..c31f8482 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/nvhost.h> | 22 | #include <linux/nvhost.h> |
23 | #include <linux/scatterlist.h> | 23 | #include <linux/scatterlist.h> |
24 | #include <linux/nvmap.h> | 24 | #include <linux/nvmap.h> |
25 | #include <soc/tegra/chip-id.h> | ||
26 | #include <linux/vmalloc.h> | 25 | #include <linux/vmalloc.h> |
27 | #include <linux/dma-buf.h> | 26 | #include <linux/dma-buf.h> |
28 | #include <linux/dma-mapping.h> | 27 | #include <linux/dma-mapping.h> |
@@ -1543,7 +1542,6 @@ static void gk20a_vm_unmap_user(struct vm_gk20a *vm, u64 offset, | |||
1543 | struct vm_gk20a_mapping_batch *batch) | 1542 | struct vm_gk20a_mapping_batch *batch) |
1544 | { | 1543 | { |
1545 | struct device *d = dev_from_vm(vm); | 1544 | struct device *d = dev_from_vm(vm); |
1546 | int retries = 10000; /* 50 ms */ | ||
1547 | struct mapped_buffer_node *mapped_buffer; | 1545 | struct mapped_buffer_node *mapped_buffer; |
1548 | 1546 | ||
1549 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); | 1547 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); |
@@ -1556,17 +1554,19 @@ static void gk20a_vm_unmap_user(struct vm_gk20a *vm, u64 offset, | |||
1556 | } | 1554 | } |
1557 | 1555 | ||
1558 | if (mapped_buffer->flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { | 1556 | if (mapped_buffer->flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { |
1557 | struct nvgpu_timeout timeout; | ||
1558 | |||
1559 | nvgpu_mutex_release(&vm->update_gmmu_lock); | 1559 | nvgpu_mutex_release(&vm->update_gmmu_lock); |
1560 | 1560 | ||
1561 | while (retries >= 0 || !tegra_platform_is_silicon()) { | 1561 | nvgpu_timeout_init(vm->mm->g, &timeout, 10000, |
1562 | NVGPU_TIMER_RETRY_TIMER); | ||
1563 | do { | ||
1562 | if (atomic_read(&mapped_buffer->ref.refcount) == 1) | 1564 | if (atomic_read(&mapped_buffer->ref.refcount) == 1) |
1563 | break; | 1565 | break; |
1564 | retries--; | ||
1565 | udelay(5); | 1566 | udelay(5); |
1566 | } | 1567 | } while (!nvgpu_timeout_expired_msg(&timeout, |
1567 | if (retries < 0 && tegra_platform_is_silicon()) | 1568 | "sync-unmap failed on 0x%llx")); |
1568 | gk20a_err(d, "sync-unmap failed on 0x%llx", | 1569 | |
1569 | offset); | ||
1570 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); | 1570 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); |
1571 | } | 1571 | } |
1572 | 1572 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 52e5d4db..81a0aac9 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -20,7 +20,6 @@ | |||
20 | 20 | ||
21 | #include <linux/scatterlist.h> | 21 | #include <linux/scatterlist.h> |
22 | #include <linux/iommu.h> | 22 | #include <linux/iommu.h> |
23 | #include <soc/tegra/chip-id.h> | ||
24 | #include <linux/vmalloc.h> | 23 | #include <linux/vmalloc.h> |
25 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
26 | #include <linux/version.h> | 25 | #include <linux/version.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 993cef7b..85fa8ea1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2374,12 +2374,11 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) | |||
2374 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | 2374 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) |
2375 | { | 2375 | { |
2376 | struct gk20a *g = gk20a_from_pmu(pmu); | 2376 | struct gk20a *g = gk20a_from_pmu(pmu); |
2377 | struct nvgpu_timeout timeout; | ||
2377 | 2378 | ||
2378 | gk20a_dbg_fn(""); | 2379 | gk20a_dbg_fn(""); |
2379 | 2380 | ||
2380 | if (enable) { | 2381 | if (enable) { |
2381 | int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX / | ||
2382 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT; | ||
2383 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); | 2382 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); |
2384 | 2383 | ||
2385 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) | 2384 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) |
@@ -2389,6 +2388,9 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2389 | g->ops.clock_gating.blcg_pmu_load_gating_prod(g, | 2388 | g->ops.clock_gating.blcg_pmu_load_gating_prod(g, |
2390 | g->blcg_enabled); | 2389 | g->blcg_enabled); |
2391 | 2390 | ||
2391 | nvgpu_timeout_init(g, &timeout, | ||
2392 | PMU_MEM_SCRUBBING_TIMEOUT_MAX / 1000, | ||
2393 | NVGPU_TIMER_CPU_TIMER); | ||
2392 | do { | 2394 | do { |
2393 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & | 2395 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & |
2394 | (pwr_falcon_dmactl_dmem_scrubbing_m() | | 2396 | (pwr_falcon_dmactl_dmem_scrubbing_m() | |
@@ -2399,7 +2401,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2399 | return 0; | 2401 | return 0; |
2400 | } | 2402 | } |
2401 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 2403 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2402 | } while (--retries || !tegra_platform_is_silicon()); | 2404 | } while (!nvgpu_timeout_expired(&timeout)); |
2403 | 2405 | ||
2404 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 2406 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); |
2405 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); | 2407 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); |