diff options
author | Vijayakumar Subbu <vsubbu@nvidia.com> | 2016-07-28 01:29:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-29 16:17:46 -0400 |
commit | b17d9708c9e9930778de43de1edf1385acb13ebd (patch) | |
tree | fc485e96cc19575d463c61c8b80a09dd89745f3f /drivers/gpu/nvgpu/gk20a | |
parent | 27b47b1969d7d9cdd3de9fd6f0131ad357f4b0fa (diff) |
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-45
Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1205849
(cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126)
Reviewed-on: http://git-master/r/1227256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_common.h | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 38 |
7 files changed, 110 insertions, 28 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index ebe2dca4..c9f84041 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -63,6 +63,9 @@ | |||
63 | #include "hal.h" | 63 | #include "hal.h" |
64 | #include "vgpu/vgpu.h" | 64 | #include "vgpu/vgpu.h" |
65 | #include "pci.h" | 65 | #include "pci.h" |
66 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
67 | #include "pstate/pstate.h" | ||
68 | #endif | ||
66 | 69 | ||
67 | #define CREATE_TRACE_POINTS | 70 | #define CREATE_TRACE_POINTS |
68 | #include <trace/events/gk20a.h> | 71 | #include <trace/events/gk20a.h> |
@@ -956,6 +959,16 @@ int gk20a_pm_finalize_poweron(struct device *dev) | |||
956 | goto done; | 959 | goto done; |
957 | } | 960 | } |
958 | 961 | ||
962 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
963 | if (g->ops.pmupstate) { | ||
964 | err = gk20a_init_pstate_support(g); | ||
965 | if (err) { | ||
966 | gk20a_err(dev, "failed to init pstates"); | ||
967 | goto done; | ||
968 | } | ||
969 | } | ||
970 | #endif | ||
971 | |||
959 | err = gk20a_init_pmu_support(g); | 972 | err = gk20a_init_pmu_support(g); |
960 | if (err) { | 973 | if (err) { |
961 | gk20a_err(dev, "failed to init gk20a pmu"); | 974 | gk20a_err(dev, "failed to init gk20a pmu"); |
@@ -968,6 +981,16 @@ int gk20a_pm_finalize_poweron(struct device *dev) | |||
968 | goto done; | 981 | goto done; |
969 | } | 982 | } |
970 | 983 | ||
984 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
985 | if (g->ops.pmupstate) { | ||
986 | err = gk20a_init_pstate_pmu_support(g); | ||
987 | if (err) { | ||
988 | gk20a_err(dev, "failed to init pstates"); | ||
989 | goto done; | ||
990 | } | ||
991 | } | ||
992 | #endif | ||
993 | |||
971 | if (g->ops.pmu.mclk_init) { | 994 | if (g->ops.pmu.mclk_init) { |
972 | err = g->ops.pmu.mclk_init(g); | 995 | err = g->ops.pmu.mclk_init(g); |
973 | if (err) { | 996 | if (err) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c4744f3c..edc4a0e1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -54,6 +54,11 @@ struct acr_desc; | |||
54 | #include "debug_gk20a.h" | 54 | #include "debug_gk20a.h" |
55 | #include "sched_gk20a.h" | 55 | #include "sched_gk20a.h" |
56 | #include "gm206/bios_gm206.h" | 56 | #include "gm206/bios_gm206.h" |
57 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
58 | #include "clk/clk.h" | ||
59 | #include "perf/perf.h" | ||
60 | #endif | ||
61 | #include "gm206/bios_gm206.h" | ||
57 | 62 | ||
58 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | 63 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. |
59 | 32 ns is the resolution of ptimer. */ | 64 | 32 ns is the resolution of ptimer. */ |
@@ -607,6 +612,7 @@ struct gpu_ops { | |||
607 | } clk; | 612 | } clk; |
608 | bool privsecurity; | 613 | bool privsecurity; |
609 | bool securegpccs; | 614 | bool securegpccs; |
615 | bool pmupstate; | ||
610 | struct { | 616 | struct { |
611 | const struct regop_offset_range* ( | 617 | const struct regop_offset_range* ( |
612 | *get_global_whitelist_ranges)(void); | 618 | *get_global_whitelist_ranges)(void); |
@@ -717,6 +723,7 @@ struct nvgpu_bios { | |||
717 | 723 | ||
718 | struct bit_token *perf_token; | 724 | struct bit_token *perf_token; |
719 | struct bit_token *clock_token; | 725 | struct bit_token *clock_token; |
726 | struct bit_token *virt_token; | ||
720 | u32 expansion_rom_offset; | 727 | u32 expansion_rom_offset; |
721 | }; | 728 | }; |
722 | 729 | ||
@@ -746,6 +753,10 @@ struct gk20a { | |||
746 | struct pmu_gk20a pmu; | 753 | struct pmu_gk20a pmu; |
747 | struct acr_desc acr; | 754 | struct acr_desc acr; |
748 | struct cooling_device_gk20a gk20a_cdev; | 755 | struct cooling_device_gk20a gk20a_cdev; |
756 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
757 | struct clk_pmupstate clk_pmu; | ||
758 | struct perf_pmupstate perf_pmu; | ||
759 | #endif | ||
749 | 760 | ||
750 | #ifdef CONFIG_DEBUG_FS | 761 | #ifdef CONFIG_DEBUG_FS |
751 | struct railgate_stats pstats; | 762 | struct railgate_stats pstats; |
@@ -992,6 +1003,7 @@ enum gk20a_dbg_categories { | |||
992 | gpu_dbg_map_v = BIT(14), /* verbose mem mappings */ | 1003 | gpu_dbg_map_v = BIT(14), /* verbose mem mappings */ |
993 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ | 1004 | gpu_dbg_sema = BIT(15), /* semaphore debugging */ |
994 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ | 1005 | gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */ |
1006 | gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */ | ||
995 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ | 1007 | gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */ |
996 | }; | 1008 | }; |
997 | 1009 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 550dffa6..b1e94d7d 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -142,6 +142,7 @@ int gk20a_init_hal(struct gk20a *g) | |||
142 | *gops = gk20a_ops; | 142 | *gops = gk20a_ops; |
143 | gops->privsecurity = 0; | 143 | gops->privsecurity = 0; |
144 | gops->securegpccs = 0; | 144 | gops->securegpccs = 0; |
145 | gops->pmupstate = false; | ||
145 | gk20a_init_mc(gops); | 146 | gk20a_init_mc(gops); |
146 | gk20a_init_ltc(gops); | 147 | gk20a_init_ltc(gops); |
147 | gk20a_init_gr_ops(gops); | 148 | gk20a_init_gr_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index aa10661c..d256f6d2 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h | |||
@@ -458,6 +458,29 @@ enum { | |||
458 | PMU_PG_ELPG_CMD_UNFREEZE, | 458 | PMU_PG_ELPG_CMD_UNFREEZE, |
459 | }; | 459 | }; |
460 | 460 | ||
461 | enum { | ||
462 | PMU_PG_CMD_ID_ELPG_CMD = 0, | ||
463 | PMU_PG_CMD_ID_ENG_BUF_LOAD, | ||
464 | PMU_PG_CMD_ID_ENG_BUF_UNLOAD, | ||
465 | PMU_PG_CMD_ID_PG_STAT, | ||
466 | PMU_PG_CMD_ID_PG_LOG_INIT, | ||
467 | PMU_PG_CMD_ID_PG_LOG_FLUSH, | ||
468 | PMU_PG_CMD_ID_PG_PARAM, | ||
469 | PMU_PG_CMD_ID_ELPG_INIT, | ||
470 | PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, | ||
471 | PMU_PG_CMD_ID_ELPG_ABORT_POLL, | ||
472 | PMU_PG_CMD_ID_ELPG_PWR_UP, | ||
473 | PMU_PG_CMD_ID_ELPG_DISALLOW, | ||
474 | PMU_PG_CMD_ID_ELPG_ALLOW, | ||
475 | PMU_PG_CMD_ID_AP, | ||
476 | RM_PMU_PG_CMD_ID_PSI, | ||
477 | RM_PMU_PG_CMD_ID_CG, | ||
478 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | ||
479 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | ||
480 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | ||
481 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE | ||
482 | }; | ||
483 | |||
461 | struct pmu_pg_cmd_elpg_cmd { | 484 | struct pmu_pg_cmd_elpg_cmd { |
462 | u8 cmd_type; | 485 | u8 cmd_type; |
463 | u8 engine_id; | 486 | u8 engine_id; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h index 76b37cf7..de37caeb 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_common.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_common.h | |||
@@ -95,6 +95,8 @@ struct flcn_u64 { | |||
95 | u32 hi; | 95 | u32 hi; |
96 | }; | 96 | }; |
97 | 97 | ||
98 | #define nv_flcn_u64 flcn_u64 | ||
99 | |||
98 | struct flcn_mem_desc_v0 { | 100 | struct flcn_mem_desc_v0 { |
99 | struct flcn_u64 address; | 101 | struct flcn_u64 address; |
100 | u32 params; | 102 | u32 params; |
@@ -132,6 +134,8 @@ struct pmu_allocation_v3 { | |||
132 | } alloc; | 134 | } alloc; |
133 | }; | 135 | }; |
134 | 136 | ||
137 | #define nv_pmu_allocation pmu_allocation_v3 | ||
138 | |||
135 | struct pmu_hdr { | 139 | struct pmu_hdr { |
136 | u8 unit_id; | 140 | u8 unit_id; |
137 | u8 size; | 141 | u8 size; |
@@ -142,4 +146,36 @@ struct pmu_hdr { | |||
142 | #define nv_pmu_hdr pmu_hdr | 146 | #define nv_pmu_hdr pmu_hdr |
143 | typedef u8 flcn_status; | 147 | typedef u8 flcn_status; |
144 | 148 | ||
145 | #endif /*__PMU_COMMON_H__*/ | 149 | #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) |
150 | |||
151 | /*! | ||
152 | * Falcon PMU DMA's minimum size in bytes. | ||
153 | */ | ||
154 | #define PMU_DMA_MIN_READ_SIZE_BYTES 16 | ||
155 | #define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 | ||
156 | |||
157 | #define PMU_FB_COPY_RW_ALIGNMENT \ | ||
158 | (PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES ? \ | ||
159 | PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) | ||
160 | |||
161 | /*! | ||
162 | * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned | ||
163 | * data structures to issue DMA read/write operations. | ||
164 | */ | ||
165 | #define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ | ||
166 | union name##_aligned { \ | ||
167 | struct name data; \ | ||
168 | u8 pad[ALIGN_UP(sizeof(struct name), \ | ||
169 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
170 | } | ||
171 | |||
172 | #define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ | ||
173 | union name##_aligned { \ | ||
174 | union name data; \ | ||
175 | u8 pad[ALIGN_UP(sizeof(union name), \ | ||
176 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
177 | } | ||
178 | |||
179 | #define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) | ||
180 | |||
181 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f041c9c1..13d3ec78 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3756,9 +3756,6 @@ static int pmu_response_handle(struct pmu_gk20a *pmu, | |||
3756 | } | 3756 | } |
3757 | if (pv->pmu_allocation_get_dmem_size(pmu, | 3757 | if (pv->pmu_allocation_get_dmem_size(pmu, |
3758 | pv->get_pmu_seq_out_a_ptr(seq)) != 0) { | 3758 | pv->get_pmu_seq_out_a_ptr(seq)) != 0) { |
3759 | gk20a_err(dev_from_gk20a(g), "dmem offs %x size %x\n", pv->pmu_allocation_get_dmem_offset(pmu,pv->get_pmu_seq_out_a_ptr(seq)), pv->pmu_allocation_get_dmem_size(pmu, | ||
3760 | pv->get_pmu_seq_out_a_ptr(seq))); | ||
3761 | gk20a_err(dev_from_gk20a(g), "copying to %p \n", seq->out_payload); | ||
3762 | pmu_copy_from_dmem(pmu, | 3759 | pmu_copy_from_dmem(pmu, |
3763 | pv->pmu_allocation_get_dmem_offset(pmu, | 3760 | pv->pmu_allocation_get_dmem_offset(pmu, |
3764 | pv->get_pmu_seq_out_a_ptr(seq)), | 3761 | pv->get_pmu_seq_out_a_ptr(seq)), |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index f0e5d3cf..fd27ab5c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -23,6 +23,9 @@ | |||
23 | 23 | ||
24 | #include "pmu_api.h" | 24 | #include "pmu_api.h" |
25 | #include "pmu_common.h" | 25 | #include "pmu_common.h" |
26 | #include "pmuif/gpmuifboardobj.h" | ||
27 | #include "pmuif/gpmuifclk.h" | ||
28 | #include "pmuif/gpmuifperf.h" | ||
26 | 29 | ||
27 | /* defined by pmu hw spec */ | 30 | /* defined by pmu hw spec */ |
28 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) | 31 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) |
@@ -172,8 +175,10 @@ struct pmu_ucode_desc_v1 { | |||
172 | #define PMU_UNIT_ACR (0x0A) | 175 | #define PMU_UNIT_ACR (0x0A) |
173 | #define PMU_UNIT_PERFMON_T18X (0x11) | 176 | #define PMU_UNIT_PERFMON_T18X (0x11) |
174 | #define PMU_UNIT_PERFMON (0x12) | 177 | #define PMU_UNIT_PERFMON (0x12) |
175 | #define PMU_UNIT_RC (0x1F) | 178 | #define PMU_UNIT_PERF (0x13) |
179 | #define PMU_UNIT_RC (0x1F) | ||
176 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) | 180 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) |
181 | #define PMU_UNIT_CLK (0x1C) | ||
177 | 182 | ||
178 | #define PMU_UNIT_END (0x23) | 183 | #define PMU_UNIT_END (0x23) |
179 | 184 | ||
@@ -295,29 +300,6 @@ struct pmu_rc_msg { | |||
295 | struct pmu_rc_msg_unhandled_cmd unhandled_cmd; | 300 | struct pmu_rc_msg_unhandled_cmd unhandled_cmd; |
296 | }; | 301 | }; |
297 | 302 | ||
298 | enum { | ||
299 | PMU_PG_CMD_ID_ELPG_CMD = 0, | ||
300 | PMU_PG_CMD_ID_ENG_BUF_LOAD, | ||
301 | PMU_PG_CMD_ID_ENG_BUF_UNLOAD, | ||
302 | PMU_PG_CMD_ID_PG_STAT, | ||
303 | PMU_PG_CMD_ID_PG_LOG_INIT, | ||
304 | PMU_PG_CMD_ID_PG_LOG_FLUSH, | ||
305 | PMU_PG_CMD_ID_PG_PARAM, | ||
306 | PMU_PG_CMD_ID_ELPG_INIT, | ||
307 | PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, | ||
308 | PMU_PG_CMD_ID_ELPG_ABORT_POLL, | ||
309 | PMU_PG_CMD_ID_ELPG_PWR_UP, | ||
310 | PMU_PG_CMD_ID_ELPG_DISALLOW, | ||
311 | PMU_PG_CMD_ID_ELPG_ALLOW, | ||
312 | PMU_PG_CMD_ID_AP, | ||
313 | RM_PMU_PG_CMD_ID_PSI, | ||
314 | RM_PMU_PG_CMD_ID_CG, | ||
315 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | ||
316 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | ||
317 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | ||
318 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE | ||
319 | }; | ||
320 | |||
321 | /***************************** ACR ERROR CODES ******************************/ | 303 | /***************************** ACR ERROR CODES ******************************/ |
322 | /*! | 304 | /*! |
323 | * Error codes used in PMU-ACR Task | 305 | * Error codes used in PMU-ACR Task |
@@ -369,6 +351,9 @@ struct pmu_cmd { | |||
369 | struct pmu_zbc_cmd zbc; | 351 | struct pmu_zbc_cmd zbc; |
370 | struct pmu_acr_cmd acr; | 352 | struct pmu_acr_cmd acr; |
371 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; | 353 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; |
354 | struct nv_pmu_boardobj_cmd boardobj; | ||
355 | struct nv_pmu_perf_cmd perf; | ||
356 | struct nv_pmu_clk_cmd clk; | ||
372 | } cmd; | 357 | } cmd; |
373 | }; | 358 | }; |
374 | 359 | ||
@@ -381,6 +366,9 @@ struct pmu_msg { | |||
381 | struct pmu_rc_msg rc; | 366 | struct pmu_rc_msg rc; |
382 | struct pmu_acr_msg acr; | 367 | struct pmu_acr_msg acr; |
383 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; | 368 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; |
369 | struct nv_pmu_boardobj_msg boardobj; | ||
370 | struct nv_pmu_perf_msg perf; | ||
371 | struct nv_pmu_clk_msg clk; | ||
384 | } msg; | 372 | } msg; |
385 | }; | 373 | }; |
386 | 374 | ||
@@ -813,4 +801,6 @@ int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | |||
813 | u32 size); | 801 | u32 size); |
814 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 802 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, |
815 | u32 size); | 803 | u32 size); |
804 | |||
805 | void print_vbios_table(u8 *msg, u8 *buff, int size); | ||
816 | #endif /*__PMU_GK20A_H__*/ | 806 | #endif /*__PMU_GK20A_H__*/ |