gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPS

NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was
resident in engine or not.

Regops are broken down into batches of 128 and each batch is executed
together. Since there only 32 bits were available in IOCTL args, returning
is ctx was resident isn't possible for all batches.
Hence return if the ctx was resident for the first batch.

Bug 200445575

Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812975
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 17 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c98fec48..03510a16 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1133,7 +1133,8 @@ struct gpu_ops {
         struct {
                 int (*exec_regops)(struct dbg_session_gk20a *dbg_s,
                             struct nvgpu_dbg_reg_op *ops,
-                            u64 num_ops);
+                            u64 num_ops,
+                            bool *is_current_ctx);
                 const struct regop_offset_range* (
                                 *get_global_whitelist_ranges)(void);
                 u64 (*get_global_whitelist_ranges_count)(void);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a40d93fd..f3b580e4 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
                           struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
-                          u32 num_ctx_wr_ops, u32 num_ctx_rd_ops)
+                          u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
+                          bool *is_curr_ctx)
 {
         struct gk20a *g = ch->g;
         int err, tmp_err;
@@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
         }
 
         ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch);
-
+        if (is_curr_ctx != NULL) {
+                *is_curr_ctx = ch_is_curr_ctx;
+        }
         nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d",
                   ch_is_curr_ctx);
 
@@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
                 i++;
         }
 
-        err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0);
+        err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
         if (err) {
                 nvgpu_err(g, "Failed to access register");
         }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 4f83bba3..617aad34 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -616,7 +616,8 @@ int gk20a_gr_suspend(struct gk20a *g);
 struct nvgpu_dbg_reg_op;
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
                           struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
-                          u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
+                          u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
+                          bool *is_curr_ctx);
 int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
                             struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
                             u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index 80d27c25..0aec4f86 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -89,7 +89,8 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
                       struct nvgpu_dbg_reg_op *ops,
-                      u64 num_ops)
+                      u64 num_ops,
+                      bool *is_current_ctx)
 {
         int err = 0;
         unsigned int i;
@@ -219,7 +220,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 
         if (ctx_wr_count | ctx_rd_count) {
                 err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops,
-                                            ctx_wr_count, ctx_rd_count);
+                                            ctx_wr_count, ctx_rd_count,
+                                            is_current_ctx);
                 if (err) {
                         nvgpu_warn(g, "failed to perform ctx ops\n");
                         goto clean_up;
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
index 0fb108a4..96705879 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -77,7 +77,8 @@ struct regop_offset_range {
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
                       struct nvgpu_dbg_reg_op *ops,
-                      u64 num_ops);
+                      u64 num_ops,
+                      bool *is_current_ctx);
 
 /* turn seriously unwieldy names -> something shorter */
 #define REGOP(x) NVGPU_DBG_REG_OP_##x