gpu: nvgpu: T186 perfmon ID update

Change-Id: Iec6aac4027c8079d10e6d09bb145fa7a37d1679b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/779696
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 35 insertions, 34 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 77c5da0a..2236e76c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -31,6 +31,10 @@
 #include "hw_pwr_gk20a.h"
 #include "hw_top_gk20a.h"
 
+#ifdef CONFIG_ARCH_TEGRA_18x_SOC
+#include "nvgpu_gpuid_t18x.h"
+#endif
+
 #define GK20A_PMU_UCODE_IMAGE   "gpmu_ucode.bin"
 
 #define gk20a_dbg_pmu(fmt, arg...) \
@@ -2810,6 +2814,30 @@ static int pmu_init_powergating(struct gk20a *g)
         return 0;
 }
 
+static u8 get_perfmon_id(struct pmu_gk20a *pmu)
+{
+        struct gk20a *g = gk20a_from_pmu(pmu);
+        u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+        u8 unit_id;
+
+        switch (ver) {
+        case GK20A_GPUID_GK20A:
+        case GK20A_GPUID_GM20B:
+                unit_id = PMU_UNIT_PERFMON;
+                break;
+#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
+        case TEGRA_18x_GPUID:
+                unit_id = PMU_UNIT_PERFMON_T18X;
+                break;
+#endif
+        default:
+                gk20a_err(&g->dev->dev, "no support for %x", ver);
+                BUG();
+        }
+
+        return unit_id;
+}
+
 static int pmu_init_perfmon(struct pmu_gk20a *pmu)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
@@ -2878,7 +2906,7 @@ static int pmu_init_perfmon(struct pmu_gk20a *pmu)
 
         /* init PERFMON */
         memset(&cmd, 0, sizeof(struct pmu_cmd));
-        cmd.hdr.unit_id = PMU_UNIT_PERFMON;
+        cmd.hdr.unit_id = get_perfmon_id(pmu);
         cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_init_size();
         cmd.cmd.perfmon.cmd_type = PMU_PERFMON_CMD_ID_INIT;
         /* buffer to save counter values for pmu perfmon */
@@ -3185,7 +3213,7 @@ static int pmu_perfmon_start_sampling(struct pmu_gk20a *pmu)
 
         /* PERFMON Start */
         memset(&cmd, 0, sizeof(struct pmu_cmd));
-        cmd.hdr.unit_id = PMU_UNIT_PERFMON;
+        cmd.hdr.unit_id = get_perfmon_id(pmu);
         cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_start_size();
         pv->perfmon_start_set_cmd_type(&cmd.cmd.perfmon,
                 PMU_PERFMON_CMD_ID_START);
@@ -3227,7 +3255,7 @@ static int pmu_perfmon_stop_sampling(struct pmu_gk20a *pmu)
 
         /* PERFMON Stop */
         memset(&cmd, 0, sizeof(struct pmu_cmd));
-        cmd.hdr.unit_id = PMU_UNIT_PERFMON;
+        cmd.hdr.unit_id = get_perfmon_id(pmu);
         cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_perfmon_cmd_stop);
         cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP;
 
@@ -3278,6 +3306,7 @@ static int pmu_handle_event(struct pmu_gk20a *pmu, struct pmu_msg *msg)
 
         switch (msg->hdr.unit_id) {
         case PMU_UNIT_PERFMON:
+        case PMU_UNIT_PERFMON_T18X:
                 err = pmu_handle_perfmon_event(pmu, &msg->msg.perfmon);
                 break;
         default:
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 6676c2e5..3dd16ec4 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -428,40 +428,12 @@ struct pmu_ucode_desc {
 };
 
 #define PMU_UNIT_REWIND         (0x00)
-#define PMU_UNIT_I2C            (0x01)
-#define PMU_UNIT_SEQ            (0x02)
-#define PMU_UNIT_PG             (0x03)
-#define PMU_UNIT_AVAILABLE1     (0x04)
-#define PMU_UNIT_AVAILABLE2     (0x05)
-#define PMU_UNIT_MEM            (0x06)
+#define PMU_UNIT_PG                     (0x03)
 #define PMU_UNIT_INIT           (0x07)
-#define PMU_UNIT_FBBA           (0x08)
-#define PMU_UNIT_DIDLE          (0x09)
 #define PMU_UNIT_ACR            (0x0A)
-#define PMU_UNIT_AVAILABLE4     (0x0B)
-#define PMU_UNIT_HDCP_MAIN      (0x0C)
-#define PMU_UNIT_HDCP_V         (0x0D)
-#define PMU_UNIT_HDCP_SRM       (0x0E)
-#define PMU_UNIT_NVDPS          (0x0F)
-#define PMU_UNIT_DEINIT         (0x10)
-#define PMU_UNIT_AVAILABLE5     (0x11)
+#define PMU_UNIT_PERFMON_T18X   (0x11)
 #define PMU_UNIT_PERFMON        (0x12)
-#define PMU_UNIT_FAN            (0x13)
-#define PMU_UNIT_PBI            (0x14)
-#define PMU_UNIT_ISOBLIT        (0x15)
-#define PMU_UNIT_DETACH         (0x16)
-#define PMU_UNIT_DISP           (0x17)
-#define PMU_UNIT_HDCP           (0x18)
-#define PMU_UNIT_REGCACHE       (0x19)
-#define PMU_UNIT_SYSMON         (0x1A)
-#define PMU_UNIT_THERM          (0x1B)
-#define PMU_UNIT_PMGR           (0x1C)
-#define PMU_UNIT_PERF           (0x1D)
-#define PMU_UNIT_PCM            (0x1E)
-#define PMU_UNIT_RC             (0x1F)
-#define PMU_UNIT_NULL           (0x20)
-#define PMU_UNIT_LOGGER         (0x21)
-#define PMU_UNIT_SMBPBI         (0x22)
+#define PMU_UNIT_RC                     (0x1F)
 #define PMU_UNIT_END            (0x23)
 
 #define PMU_UNIT_TEST_START     (0xFE)