gpu: nvgpu: add HAL to set ppriv timeouts

Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific
ppriv timeouts
Set this HAL for all supported GPUs for now

Jira NVGPUT-35

Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699314
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 18 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
index 81a5facc..ab75e8d7 100644
--- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
@@ -34,6 +34,9 @@
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
 
 void gk20a_bus_init_hw(struct gk20a *g)
 {
@@ -172,3 +175,14 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
 
         return 0;
 }
+
+void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g)
+{
+        /*
+         * Bug 1340570: increase the clock timeout to avoid potential
+         * operation failure at high gpcclk rate. Default values are 0x400.
+         */
+        nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
+        nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
+        nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
+}
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.h b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h
index 1f81a4b0..8c07d1fe 100644
--- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h
@@ -32,5 +32,6 @@ void gk20a_bus_isr(struct gk20a *g);
 int gk20a_read_ptimer(struct gk20a *g, u64 *value);
 void gk20a_bus_init_hw(struct gk20a *g);
 int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst);
+void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g);
 
 #endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 2e7bd4a5..bb0b572f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1094,6 +1094,7 @@ struct gpu_ops {
                         u32 source_id, u32 count,
                         struct nvgpu_cpu_time_correlation_sample *);
                 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
+                void (*set_ppriv_timeout_settings)(struct gk20a *g);
         } bus;
 
         struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index ed1f9af9..51bb2551 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -53,9 +53,6 @@
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
@@ -4489,12 +4486,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gr_gk20a_zcull_init_hw(g, gr);
 
-        /* Bug 1340570: increase the clock timeout to avoid potential
-         * operation failure at high gpcclk rate. Default values are 0x400.
-         */
-        gk20a_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
-        gk20a_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
-        gk20a_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
+        if (g->ops.bus.set_ppriv_timeout_settings)
+                g->ops.bus.set_ppriv_timeout_settings(g);
 
         /* enable fifo access */
         gk20a_writel(g, gr_gpfifo_ctl_r(),