nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.

pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.

JIRA GV11B-30

Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 25 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 6ca5855a..7df2c2e0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -618,6 +618,10 @@ struct gpu_ops {
                 int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
                 int (*pmu_nsbootstrap)(struct pmu_gk20a *pmu);
                 int (*pmu_setup_elpg)(struct gk20a *g);
+                u32 (*pmu_get_queue_head)(u32 i);
+                u32 (*pmu_get_queue_head_size)(void);
+                u32 (*pmu_get_queue_tail_size)(void);
+                u32 (*pmu_get_queue_tail)(u32 i);
                 int (*init_wpr_region)(struct gk20a *g);
                 int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
                 void (*write_dmatrfbase)(struct gk20a *g, u32 addr);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index c9eb25fe..26ed3a49 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2625,21 +2625,25 @@ static int pmu_queue_head(struct pmu_gk20a *pmu, struct pmu_queue *queue,
                         u32 *head, bool set)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
+        u32 queue_head_size = 0;
 
-        BUG_ON(!head);
+        if (g->ops.pmu.pmu_get_queue_head_size)
+                queue_head_size = g->ops.pmu.pmu_get_queue_head_size();
+
+        BUG_ON(!head || !queue_head_size);
 
         if (PMU_IS_COMMAND_QUEUE(queue->id)) {
 
-                if (queue->index >= pwr_pmu_queue_head__size_1_v())
+                if (queue->index >= queue_head_size)
                         return -EINVAL;
 
                 if (!set)
                         *head = pwr_pmu_queue_head_address_v(
                                 gk20a_readl(g,
-                                        pwr_pmu_queue_head_r(queue->index)));
+                                g->ops.pmu.pmu_get_queue_head(queue->index)));
                 else
                         gk20a_writel(g,
-                                pwr_pmu_queue_head_r(queue->index),
+                                g->ops.pmu.pmu_get_queue_head(queue->index),
                                 pwr_pmu_queue_head_address_f(*head));
         } else {
                 if (!set)
@@ -2658,21 +2662,25 @@ static int pmu_queue_tail(struct pmu_gk20a *pmu, struct pmu_queue *queue,
                         u32 *tail, bool set)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
+        u32 queue_tail_size = 0;
+
+        if (g->ops.pmu.pmu_get_queue_tail_size)
+                queue_tail_size = g->ops.pmu.pmu_get_queue_tail_size();
 
-        BUG_ON(!tail);
+        BUG_ON(!tail || !queue_tail_size);
 
         if (PMU_IS_COMMAND_QUEUE(queue->id)) {
 
-                if (queue->index >= pwr_pmu_queue_tail__size_1_v())
+                if (queue->index >= queue_tail_size)
                         return -EINVAL;
 
                 if (!set)
                         *tail = pwr_pmu_queue_tail_address_v(
-                                gk20a_readl(g,
-                                        pwr_pmu_queue_tail_r(queue->index)));
+                        gk20a_readl(g,
+                                g->ops.pmu.pmu_get_queue_tail(queue->index)));
                 else
                         gk20a_writel(g,
-                                pwr_pmu_queue_tail_r(queue->index),
+                                g->ops.pmu.pmu_get_queue_tail(queue->index),
                                 pwr_pmu_queue_tail_address_f(*tail));
 
         } else {
@@ -3445,6 +3453,10 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.prepare_ucode = gk20a_prepare_ucode;
         gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
         gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
+        gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r;
+        gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v;
+        gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r;
+        gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v;
         gops->pmu.pmu_setup_elpg = NULL;
         gops->pmu.init_wpr_region = NULL;
         gops->pmu.load_lsfalcon_ucode = NULL;