diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-14 18:54:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-02 06:06:08 -0400 |
commit | a30924340f879db1f2857e066b919eeecf03c693 (patch) | |
tree | fe92f504d70854ab81819c7ab7d2a54c2d676836 /drivers/gpu/nvgpu/gk20a | |
parent | 4d1237f132163cb0a397a5407570377e77d70b1b (diff) |
gpu: nvgpu: Add new flag support_pmu to gk20a
Add new flag support_pmu to struct gk20a at probe time, and access it
from gk20a instead of support_gk20a_pmu() which depends on struct
device *.
JIRA NVGPU-16
Change-Id: I721f1a532e949c98346086abdc2630a8df6eba7b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463546
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 12 |
5 files changed, 16 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b96adc5a..4129e407 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1231,7 +1231,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1231 | nvgpu_err(g, "unsupported engine_id %d", engine_id); | 1231 | nvgpu_err(g, "unsupported engine_id %d", engine_id); |
1232 | 1232 | ||
1233 | if (engine_enum == ENGINE_GR_GK20A) { | 1233 | if (engine_enum == ENGINE_GR_GK20A) { |
1234 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) | 1234 | if (g->support_pmu && g->elpg_enabled) |
1235 | gk20a_pmu_disable_elpg(g); | 1235 | gk20a_pmu_disable_elpg(g); |
1236 | /* resetting engine will alter read/write index. | 1236 | /* resetting engine will alter read/write index. |
1237 | * need to flush circular buffer before re-enabling FECS. | 1237 | * need to flush circular buffer before re-enabling FECS. |
@@ -1244,7 +1244,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1244 | /* resetting engine using mc_enable_r() is not | 1244 | /* resetting engine using mc_enable_r() is not |
1245 | enough, we do full init sequence */ | 1245 | enough, we do full init sequence */ |
1246 | gk20a_gr_reset(g); | 1246 | gk20a_gr_reset(g); |
1247 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) | 1247 | if (g->support_pmu && g->elpg_enabled) |
1248 | gk20a_pmu_enable_elpg(g); | 1248 | gk20a_pmu_enable_elpg(g); |
1249 | } | 1249 | } |
1250 | if ((engine_enum == ENGINE_GRCE_GK20A) || | 1250 | if ((engine_enum == ENGINE_GRCE_GK20A) || |
@@ -1479,7 +1479,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1479 | g->fifo.deferred_reset_pending = false; | 1479 | g->fifo.deferred_reset_pending = false; |
1480 | 1480 | ||
1481 | /* Disable power management */ | 1481 | /* Disable power management */ |
1482 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) | 1482 | if (g->support_pmu && g->elpg_enabled) |
1483 | gk20a_pmu_disable_elpg(g); | 1483 | gk20a_pmu_disable_elpg(g); |
1484 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) | 1484 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) |
1485 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, | 1485 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, |
@@ -1678,7 +1678,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1678 | gr_gpfifo_ctl_semaphore_access_enabled_f()); | 1678 | gr_gpfifo_ctl_semaphore_access_enabled_f()); |
1679 | 1679 | ||
1680 | /* It is safe to enable ELPG again. */ | 1680 | /* It is safe to enable ELPG again. */ |
1681 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) | 1681 | if (g->support_pmu && g->elpg_enabled) |
1682 | gk20a_pmu_enable_elpg(g); | 1682 | gk20a_pmu_enable_elpg(g); |
1683 | return verbose; | 1683 | return verbose; |
1684 | } | 1684 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 6c846251..71ff8d3e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1005,6 +1005,8 @@ struct gk20a { | |||
1005 | /* Debugfs knob for forcing syncpt support off in runtime. */ | 1005 | /* Debugfs knob for forcing syncpt support off in runtime. */ |
1006 | u32 disable_syncpoints; | 1006 | u32 disable_syncpoints; |
1007 | 1007 | ||
1008 | bool support_pmu; | ||
1009 | |||
1008 | u32 emc3d_ratio; | 1010 | u32 emc3d_ratio; |
1009 | 1011 | ||
1010 | #ifdef CONFIG_DEBUG_FS | 1012 | #ifdef CONFIG_DEBUG_FS |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 57cd266d..ac03c1e5 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3231,7 +3231,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3231 | u32 lockboost_mask; | 3231 | u32 lockboost_mask; |
3232 | u32 lockboost; | 3232 | u32 lockboost; |
3233 | 3233 | ||
3234 | if (support_gk20a_pmu(g->dev)) { | 3234 | if (g->support_pmu) { |
3235 | err = gk20a_pmu_disable_elpg(g); | 3235 | err = gk20a_pmu_disable_elpg(g); |
3236 | if (err) { | 3236 | if (err) { |
3237 | nvgpu_err(g, | 3237 | nvgpu_err(g, |
@@ -3281,7 +3281,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3281 | 3281 | ||
3282 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; | 3282 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; |
3283 | 3283 | ||
3284 | if (support_gk20a_pmu(g->dev)) | 3284 | if (g->support_pmu) |
3285 | gk20a_pmu_enable_elpg(g); | 3285 | gk20a_pmu_enable_elpg(g); |
3286 | } | 3286 | } |
3287 | 3287 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 24bfb3b7..06ce96e7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -544,14 +544,14 @@ void gk20a_gr_clear_sm_hww(struct gk20a *g, | |||
544 | #define gr_gk20a_elpg_protected_call(g, func) \ | 544 | #define gr_gk20a_elpg_protected_call(g, func) \ |
545 | ({ \ | 545 | ({ \ |
546 | int err = 0; \ | 546 | int err = 0; \ |
547 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) {\ | 547 | if (g->support_pmu && g->elpg_enabled) {\ |
548 | err = gk20a_pmu_disable_elpg(g); \ | 548 | err = gk20a_pmu_disable_elpg(g); \ |
549 | if (err) \ | 549 | if (err) \ |
550 | gk20a_pmu_enable_elpg(g); \ | 550 | gk20a_pmu_enable_elpg(g); \ |
551 | } \ | 551 | } \ |
552 | if (!err) { \ | 552 | if (!err) { \ |
553 | err = func; \ | 553 | err = func; \ |
554 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) \ | 554 | if (g->support_pmu && g->elpg_enabled) \ |
555 | gk20a_pmu_enable_elpg(g); \ | 555 | gk20a_pmu_enable_elpg(g); \ |
556 | } \ | 556 | } \ |
557 | err; \ | 557 | err; \ |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 98513511..26ce66f1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3548,7 +3548,7 @@ int gk20a_init_pmu_support(struct gk20a *g) | |||
3548 | if (err) | 3548 | if (err) |
3549 | return err; | 3549 | return err; |
3550 | 3550 | ||
3551 | if (support_gk20a_pmu(g->dev)) { | 3551 | if (g->support_pmu) { |
3552 | err = gk20a_init_pmu_setup_sw(g); | 3552 | err = gk20a_init_pmu_setup_sw(g); |
3553 | if (err) | 3553 | if (err) |
3554 | return err; | 3554 | return err; |
@@ -4945,7 +4945,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4945 | if (g->ops.pmu.pmu_lpwr_enable_pg) | 4945 | if (g->ops.pmu.pmu_lpwr_enable_pg) |
4946 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, | 4946 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, |
4947 | true); | 4947 | true); |
4948 | } else if (support_gk20a_pmu(g->dev)) | 4948 | } else if (g->support_pmu) |
4949 | status = gk20a_pmu_enable_elpg(g); | 4949 | status = gk20a_pmu_enable_elpg(g); |
4950 | } else if (enable_pg == false) { | 4950 | } else if (enable_pg == false) { |
4951 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 4951 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -4955,7 +4955,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4955 | if (g->ops.pmu.pmu_lpwr_disable_pg) | 4955 | if (g->ops.pmu.pmu_lpwr_disable_pg) |
4956 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, | 4956 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, |
4957 | true); | 4957 | true); |
4958 | } else if (support_gk20a_pmu(g->dev)) | 4958 | } else if (g->support_pmu) |
4959 | status = gk20a_pmu_disable_elpg(g); | 4959 | status = gk20a_pmu_disable_elpg(g); |
4960 | } | 4960 | } |
4961 | 4961 | ||
@@ -5008,7 +5008,7 @@ int gk20a_pmu_enable_elpg(struct gk20a *g) | |||
5008 | 5008 | ||
5009 | gk20a_dbg_fn(""); | 5009 | gk20a_dbg_fn(""); |
5010 | 5010 | ||
5011 | if (!support_gk20a_pmu(g->dev)) | 5011 | if (!g->support_pmu) |
5012 | return ret; | 5012 | return ret; |
5013 | 5013 | ||
5014 | nvgpu_mutex_acquire(&pmu->elpg_mutex); | 5014 | nvgpu_mutex_acquire(&pmu->elpg_mutex); |
@@ -5070,7 +5070,7 @@ int gk20a_pmu_disable_elpg(struct gk20a *g) | |||
5070 | if (g->ops.pmu.pmu_pg_supported_engines_list) | 5070 | if (g->ops.pmu.pmu_pg_supported_engines_list) |
5071 | pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g); | 5071 | pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g); |
5072 | 5072 | ||
5073 | if (!support_gk20a_pmu(g->dev)) | 5073 | if (!g->support_pmu) |
5074 | return ret; | 5074 | return ret; |
5075 | 5075 | ||
5076 | nvgpu_mutex_acquire(&pmu->elpg_mutex); | 5076 | nvgpu_mutex_acquire(&pmu->elpg_mutex); |
@@ -5188,7 +5188,7 @@ int gk20a_pmu_destroy(struct gk20a *g) | |||
5188 | 5188 | ||
5189 | gk20a_dbg_fn(""); | 5189 | gk20a_dbg_fn(""); |
5190 | 5190 | ||
5191 | if (!support_gk20a_pmu(g->dev)) | 5191 | if (!g->support_pmu) |
5192 | return 0; | 5192 | return 0; |
5193 | 5193 | ||
5194 | /* make sure the pending operations are finished before we continue */ | 5194 | /* make sure the pending operations are finished before we continue */ |