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author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-21 07:43:43 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-27 13:11:27 -0400 |
commit | 9ed117dd01d60d540d430aebcd286e7bacf84930 (patch) | |
tree | fe883c4dc4213d917b6fbfc08c63fcdf8e15fc6d /drivers/gpu/nvgpu/gk20a | |
parent | 1161b650d72c1bb73fce2632e040ecc9074ba9d0 (diff) |
gpu: nvgpu: add HAL to update doorbell
Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell
register and to trigger a runlist scan
Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips
Jira NVGPUT-18
Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702114
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 0a60d46a..65750a15 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -672,6 +672,7 @@ struct gpu_ops { | |||
672 | void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id, | 672 | void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id, |
673 | u32 count, u32 buffer_index); | 673 | u32 count, u32 buffer_index); |
674 | int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); | 674 | int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); |
675 | void (*ring_channel_doorbell)(struct channel_gk20a *c); | ||
675 | } fifo; | 676 | } fifo; |
676 | struct pmu_v { | 677 | struct pmu_v { |
677 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 678 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |