gpu: nvgpu: Remove separation of t18x code

Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.

Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 38 insertions, 31 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
index f04ff56c..0d1ed5df 100644
--- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -32,9 +32,6 @@ struct gk20a_ecc_stat {
 #endif
 };
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-#include "ecc_t18x.h"
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "ecc_t19x.h"
 #endif
@@ -42,15 +39,30 @@ struct gk20a_ecc_stat {
 struct ecc_gk20a {
         /* Stats per engine */
         struct {
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-                struct ecc_gr_t18x t18x;
-#endif
+                struct gk20a_ecc_stat sm_lrf_single_err_count;
+                struct gk20a_ecc_stat sm_lrf_double_err_count;
+
+                struct gk20a_ecc_stat sm_shm_sec_count;
+                struct gk20a_ecc_stat sm_shm_sed_count;
+                struct gk20a_ecc_stat sm_shm_ded_count;
+
+                struct gk20a_ecc_stat tex_total_sec_pipe0_count;
+                struct gk20a_ecc_stat tex_total_ded_pipe0_count;
+                struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
+                struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
+                struct gk20a_ecc_stat tex_total_sec_pipe1_count;
+                struct gk20a_ecc_stat tex_total_ded_pipe1_count;
+                struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
+                struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
+
 #ifdef CONFIG_TEGRA_19x_GPU
                 struct ecc_gr_t19x t19x;
 #endif
         } gr;
 
         struct {
+                struct gk20a_ecc_stat l2_sec_count;
+                struct gk20a_ecc_stat l2_ded_count;
 #ifdef CONFIG_TEGRA_19x_GPU
                 struct ecc_ltc_t19x t19x;
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 5bdd81ac..c029e9e0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -46,9 +46,7 @@
 #include "mc_gk20a.h"
 #include "hal.h"
 #include "bus_gk20a.h"
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "pstate/pstate.h"
-#endif
 
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "nvgpu_gpuid_t19x.h"
@@ -112,10 +110,9 @@ int gk20a_prepare_poweroff(struct gk20a *g)
         if (g->ops.clk.suspend_clk_support)
                 ret |= g->ops.clk.suspend_clk_support(g);
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE))
                 gk20a_deinit_pstate_support(g);
-#endif
+
         g->power_on = false;
 
         return ret;
@@ -240,7 +237,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 }
         }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
                 err = gk20a_init_pstate_support(g);
                 if (err) {
@@ -248,7 +244,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                         goto done;
                 }
         }
-#endif
 
         if (g->ops.pmu.is_pmu_supported(g)) {
                 err = nvgpu_init_pmu_support(g);
@@ -264,7 +259,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 goto done;
         }
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
                 err = gk20a_init_pstate_pmu_support(g);
                 if (err) {
@@ -278,7 +272,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
                 nvgpu_err(g, "failed to init clk arb");
                 goto done;
         }
-#endif
 
         err = gk20a_init_therm_support(g);
         if (err) {
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fef9f498..8d8bfbec 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -72,12 +72,10 @@ struct nvgpu_ctxsw_trace_filter;
 #include "pmu_gk20a.h"
 #include "priv_ring_gk20a.h"
 #include "therm_gk20a.h"
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "clk/clk.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
 #include "therm/thrm.h"
-#endif
 #include "ecc_gk20a.h"
 
 /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
@@ -1128,12 +1126,10 @@ struct gk20a {
         struct nvgpu_pmu pmu;
         struct acr_desc acr;
         struct ecc_gk20a ecc;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
         struct clk_pmupstate clk_pmu;
         struct perf_pmupstate perf_pmu;
         struct pmgr_pmupstate pmgr_pmu;
         struct therm_pmupstate therm_pmu;
-#endif
 
 #ifdef CONFIG_DEBUG_FS
         struct railgate_stats pstats;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index f44e96a7..0df88988 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -24,9 +24,6 @@
 #ifndef GR_GK20A_H
 #define GR_GK20A_H
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-#include "gr_t18x.h"
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "gr_t19x.h"
 #endif
@@ -316,6 +313,11 @@ struct gr_gk20a {
                 } ctxsw_regs;
                 int regs_base_index;
                 bool valid;
+
+                u32 preempt_image_size;
+                bool force_preemption_gfxp;
+                bool force_preemption_cilp;
+                bool dump_ctxsw_stats_on_channel_close;
         } ctx_vars;
 
         struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */
@@ -409,9 +411,11 @@ struct gr_gk20a {
         bool sw_ready;
         bool skip_ucode_init;
 
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-        struct gr_t18x t18x;
-#endif
+        struct nvgpu_preemption_modes_rec preemption_mode_rec;
+
+        u32 fecs_feature_override_ecc_val;
+
+        int cilp_preempt_pending_chid;
 
         u32 fbp_en_mask;
         u32 *fbp_rop_l2_en_mask;
@@ -433,9 +437,15 @@ struct gr_ctx_desc {
         u32 graphics_preempt_mode;
         u32 compute_preempt_mode;
         bool boosted_ctx;
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
-        struct gr_ctx_desc_t18x t18x;
-#endif
+
+        struct nvgpu_mem preempt_ctxsw_buffer;
+        struct nvgpu_mem spill_ctxsw_buffer;
+        struct nvgpu_mem betacb_ctxsw_buffer;
+        struct nvgpu_mem pagepool_ctxsw_buffer;
+        u32 ctx_id;
+        bool ctx_id_valid;
+        bool cilp_preempt_pending;
+
 #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
         u64 virt_ctx;
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index 13e6f374..d24d4bc5 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -44,7 +44,6 @@ int gpu_init_hal(struct gk20a *g)
                 if (gm20b_init_hal(g))
                         return -ENODEV;
                 break;
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
         case NVGPU_GPUID_GP10B:
                 if (gp10b_init_hal(g))
                         return -ENODEV;
@@ -54,7 +53,6 @@ int gpu_init_hal(struct gk20a *g)
                 if (gp106_init_hal(g))
                         return -ENODEV;
                 break;
-#endif
 #ifdef CONFIG_TEGRA_19x_GPU
         case TEGRA_19x_GPUID:
                 if (TEGRA_19x_GPUID_HAL(g))
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index d8478b2d..4e3eeb51 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -589,12 +589,10 @@ int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu,
 
         switch (msg->msg_type) {
         case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION:
-#ifdef CONFIG_ARCH_TEGRA_18x_SOC
                 if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1))
                         nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu),
                                 (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD));
                 else
-#endif
                         gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d",
                                 msg->hw_slct_msg.mask);
                 break;