gpu: nvgpu: add fecs_host_int_enable hal

This will be used to enable fecs interrupts per
chip.

Change-Id: Id99412ca1a9c4caad999c3458b0e9701515db4b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642554
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 17 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8bddad11..3bc10109 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -441,6 +441,7 @@ struct gpu_ops {
                 u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g);
                 void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm,
                                          struct nvgpu_gr_ctx *gr_ctx);
+                void (*fecs_host_int_enable)(struct gk20a *g);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 68ad7bcd..c7b00500 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4344,6 +4344,16 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g)
                      gr_memfmt_hww_esr_reset_active_f());
 }
 
+void gr_gk20a_fecs_host_int_enable(struct gk20a *g)
+{
+        gk20a_writel(g, gr_fecs_host_int_enable_r(),
+                     gr_fecs_host_int_enable_ctxsw_intr1_enable_f() |
+                     gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() |
+                     gr_fecs_host_int_enable_umimp_firmware_method_enable_f() |
+                     gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
+                     gr_fecs_host_int_enable_watchdog_enable_f());
+}
+
 static int gk20a_init_gr_setup_hw(struct gk20a *g)
 {
         struct gr_gk20a *gr = &g->gr;
@@ -4407,12 +4417,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
         gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF);
 
         /* enable fecs error interrupts */
-        gk20a_writel(g, gr_fecs_host_int_enable_r(),
-                     gr_fecs_host_int_enable_ctxsw_intr1_enable_f() |
-                     gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() |
-                     gr_fecs_host_int_enable_umimp_firmware_method_enable_f() |
-                     gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
-                     gr_fecs_host_int_enable_watchdog_enable_f());
+        g->ops.gr.fecs_host_int_enable(g);
 
         g->ops.gr.enable_hww_exceptions(g);
         g->ops.gr.set_hww_esr_report_mask(g);
@@ -5124,15 +5129,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
         u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
         int ret = 0;
 
-        gk20a_dbg_fn("");
-
         if (!gr_fecs_intr)
                 return 0;
 
-        nvgpu_err(g,
-                   "unhandled fecs error interrupt 0x%08x for channel %u",
-                   gr_fecs_intr, isr_data->chid);
-
         if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) {
                 gk20a_gr_set_error_notifier(g, isr_data,
                          NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD);
@@ -5141,6 +5140,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                           gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)),
                           isr_data->data_lo);
                 ret = -1;
+        } else {
+                nvgpu_err(g,
+                   "fecs error interrupt 0x%08x for channel %u",
+                   gr_fecs_intr, isr_data->chid);
         }
 
         gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index d1c32c03..fa0a4c2d 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -732,7 +732,7 @@ static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g)
 }
 #endif
 
-
+void gr_gk20a_fecs_host_int_enable(struct gk20a *g);
 int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                 struct gr_gk20a_isr_data *isr_data);
 int gk20a_gr_lock_down_sm(struct gk20a *g,