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authorAparna Das <aparnad@nvidia.com>2018-02-15 18:39:10 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-06 17:52:21 -0500
commit98d91dd2609faadfa4aa9aafad5e295c924ae08f (patch)
tree40daaafbb2756a1defa0f299a8881799b6b0161c /drivers/gpu/nvgpu/gk20a
parentd654ab48638b0160ccef6f7be0faa8b3b3ee1fab (diff)
gpu: nvgpu: add hal op to handle post event id
The vserver variant for gr post event id needs different functionality to send interrupt to VM. Add HAL operation to allow overriding vserver usecase. Jira VQRM-2982 Change-Id: I915d089ef751023968c1e8ab181c21afeec997a5 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1658382 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c8
3 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 2c98797d..f9b9c6e6 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -2229,7 +2229,7 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
2229 struct tsg_gk20a *tsg = 2229 struct tsg_gk20a *tsg =
2230 &g->fifo.tsg[c->tsgid]; 2230 &g->fifo.tsg[c->tsgid];
2231 2231
2232 gk20a_tsg_event_id_post_event(tsg, 2232 g->ops.fifo.post_event_id(tsg,
2233 NVGPU_EVENT_ID_BLOCKING_SYNC); 2233 NVGPU_EVENT_ID_BLOCKING_SYNC);
2234 } 2234 }
2235 } 2235 }
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d9e3c97d..6f99b3f9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -610,6 +610,7 @@ struct gpu_ops {
610 void (*deinit_eng_method_buffers)(struct gk20a *g, 610 void (*deinit_eng_method_buffers)(struct gk20a *g,
611 struct tsg_gk20a *tsg); 611 struct tsg_gk20a *tsg);
612 u32 (*get_preempt_timeout)(struct gk20a *g); 612 u32 (*get_preempt_timeout)(struct gk20a *g);
613 void (*post_event_id)(struct tsg_gk20a *tsg, int event_id);
613#ifdef CONFIG_TEGRA_GK20A_NVHOST 614#ifdef CONFIG_TEGRA_GK20A_NVHOST
614 int (*alloc_syncpt_buf)(struct channel_gk20a *c, 615 int (*alloc_syncpt_buf)(struct channel_gk20a *c,
615 u32 syncpt_id, struct nvgpu_mem *syncpt_buf); 616 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 8f263e67..c64900bd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5274,7 +5274,7 @@ static int gk20a_gr_handle_semaphore_pending(struct gk20a *g,
5274 struct channel_gk20a *ch = &f->channel[isr_data->chid]; 5274 struct channel_gk20a *ch = &f->channel[isr_data->chid];
5275 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; 5275 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
5276 5276
5277 gk20a_tsg_event_id_post_event(tsg, 5277 g->ops.fifo.post_event_id(tsg,
5278 NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); 5278 NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
5279 5279
5280 nvgpu_cond_broadcast(&ch->semaphore_wq); 5280 nvgpu_cond_broadcast(&ch->semaphore_wq);
@@ -5818,14 +5818,12 @@ static int gk20a_gr_post_bpt_events(struct gk20a *g, struct channel_gk20a *ch,
5818 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) { 5818 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) {
5819 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; 5819 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
5820 5820
5821 gk20a_tsg_event_id_post_event(tsg, 5821 g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_INT);
5822 NVGPU_EVENT_ID_BPT_INT);
5823 } 5822 }
5824 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) { 5823 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) {
5825 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; 5824 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
5826 5825
5827 gk20a_tsg_event_id_post_event(tsg, 5826 g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_PAUSE);
5828 NVGPU_EVENT_ID_BPT_PAUSE);
5829 } 5827 }
5830 5828
5831 return 0; 5829 return 0;