diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2014-09-02 05:57:43 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:13 -0400 |
commit | 926cd4a2606fb37388ea79d86cde976dda5e08bc (patch) | |
tree | 4c5e54215f6203e68b473b14c6b19025294f7b42 /drivers/gpu/nvgpu/gk20a | |
parent | 48e19c6c2857047a1d0f56d98bbe48dcd4726fcd (diff) |
gpu: nvgpu: add ioctls for TSG enable/disable
Add ioctls to enable/disable/preempt a TSG
1. NVGPU_IOCTL_TSG_ENABLE
enable all the channels in a TSG
2. NVGPU_IOCTL_TSG_DISABLE
disable all the channels in a TSG
3. NVGPU_IOCTL_TSG_PREEMPT
preempt a TSG with given id
Bug 1514064
Change-Id: I2db6404b8536e872243cbe57b99e7c6d14243fa5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/494671
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 849c3f6a..67fa6508 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/anon_inodes.h> | 23 | #include <linux/anon_inodes.h> |
24 | 24 | ||
25 | #include "gk20a.h" | 25 | #include "gk20a.h" |
26 | #include "hw_ccsr_gk20a.h" | ||
26 | 27 | ||
27 | static void gk20a_tsg_release(struct kref *ref); | 28 | static void gk20a_tsg_release(struct kref *ref); |
28 | 29 | ||
@@ -226,6 +227,60 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
226 | */ | 227 | */ |
227 | break; | 228 | break; |
228 | 229 | ||
230 | case NVGPU_IOCTL_TSG_ENABLE: | ||
231 | { | ||
232 | struct channel_gk20a *ch; | ||
233 | err = gk20a_busy(g->dev); | ||
234 | if (err) { | ||
235 | gk20a_err(&g->dev->dev, | ||
236 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); | ||
237 | return err; | ||
238 | } | ||
239 | mutex_lock(&tsg->ch_list_lock); | ||
240 | list_for_each_entry(ch, &tsg->ch_list, ch_entry) { | ||
241 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | ||
242 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | ||
243 | | ccsr_channel_enable_set_true_f()); | ||
244 | } | ||
245 | mutex_unlock(&tsg->ch_list_lock); | ||
246 | gk20a_idle(g->dev); | ||
247 | break; | ||
248 | } | ||
249 | |||
250 | case NVGPU_IOCTL_TSG_DISABLE: | ||
251 | { | ||
252 | struct channel_gk20a *ch; | ||
253 | err = gk20a_busy(g->dev); | ||
254 | if (err) { | ||
255 | gk20a_err(&g->dev->dev, | ||
256 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); | ||
257 | return err; | ||
258 | } | ||
259 | mutex_lock(&tsg->ch_list_lock); | ||
260 | list_for_each_entry(ch, &tsg->ch_list, ch_entry) { | ||
261 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | ||
262 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | ||
263 | | ccsr_channel_enable_clr_true_f()); | ||
264 | } | ||
265 | mutex_unlock(&tsg->ch_list_lock); | ||
266 | gk20a_idle(g->dev); | ||
267 | break; | ||
268 | } | ||
269 | |||
270 | case NVGPU_IOCTL_TSG_PREEMPT: | ||
271 | { | ||
272 | err = gk20a_busy(g->dev); | ||
273 | if (err) { | ||
274 | gk20a_err(&g->dev->dev, | ||
275 | "failed to host gk20a for ioctl cmd: 0x%x", cmd); | ||
276 | return err; | ||
277 | } | ||
278 | /* preempt TSG */ | ||
279 | err = gk20a_fifo_preempt_tsg(g, tsg->tsgid); | ||
280 | gk20a_idle(g->dev); | ||
281 | break; | ||
282 | } | ||
283 | |||
229 | default: | 284 | default: |
230 | gk20a_err(dev_from_gk20a(g), | 285 | gk20a_err(dev_from_gk20a(g), |
231 | "unrecognized tsg gpu ioctl cmd: 0x%x", | 286 | "unrecognized tsg gpu ioctl cmd: 0x%x", |