diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-08-09 12:20:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-14 18:33:20 -0400 |
commit | 91390d857f6302f9c2923ec4188ea7e24ee537a2 (patch) | |
tree | e0884e79ea748d2c0bd384c29f805125a7b88fec /drivers/gpu/nvgpu/gk20a | |
parent | 02f9c99e4b4a452ded20978c5ee1e27b775b9224 (diff) |
gpu: nvgpu: Move therm HAL to common
Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.
Bump gk20a code to gm20b.
JIRA NVGPU-955
Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 71 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/therm_gk20a.c | 111 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/therm_gk20a.h | 31 |
7 files changed, 18 insertions, 229 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index a257d709..65bf2976 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -36,7 +36,6 @@ | |||
36 | #include "dbg_gpu_gk20a.h" | 36 | #include "dbg_gpu_gk20a.h" |
37 | #include "regops_gk20a.h" | 37 | #include "regops_gk20a.h" |
38 | 38 | ||
39 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> | ||
40 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 39 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
41 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 24cfc6ec..859a7b6a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include <nvgpu/ctxsw_trace.h> | 36 | #include <nvgpu/ctxsw_trace.h> |
37 | #include <nvgpu/soc.h> | 37 | #include <nvgpu/soc.h> |
38 | #include <nvgpu/clk_arb.h> | 38 | #include <nvgpu/clk_arb.h> |
39 | #include <nvgpu/therm.h> | ||
39 | 40 | ||
40 | #include <trace/events/gk20a.h> | 41 | #include <trace/events/gk20a.h> |
41 | 42 | ||
@@ -323,7 +324,7 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
323 | } | 324 | } |
324 | } | 325 | } |
325 | 326 | ||
326 | err = gk20a_init_therm_support(g); | 327 | err = nvgpu_init_therm_support(g); |
327 | if (err) { | 328 | if (err) { |
328 | nvgpu_err(g, "failed to init gk20a therm"); | 329 | nvgpu_err(g, "failed to init gk20a therm"); |
329 | goto done; | 330 | goto done; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 204fd371..5bb91f62 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter; | |||
69 | #include "fifo_gk20a.h" | 69 | #include "fifo_gk20a.h" |
70 | #include "tsg_gk20a.h" | 70 | #include "tsg_gk20a.h" |
71 | #include "pmu_gk20a.h" | 71 | #include "pmu_gk20a.h" |
72 | #include "therm_gk20a.h" | ||
73 | #include "clk/clk.h" | 72 | #include "clk/clk.h" |
74 | #include "perf/perf.h" | 73 | #include "perf/perf.h" |
75 | #include "pmgr/pmgr.h" | 74 | #include "pmgr/pmgr.h" |
@@ -161,6 +160,18 @@ struct nvgpu_gpfifo_userdata { | |||
161 | #define NVGPU_FB_MMU_FAULT_BUF_DISABLED 0U | 160 | #define NVGPU_FB_MMU_FAULT_BUF_DISABLED 0U |
162 | #define NVGPU_FB_MMU_FAULT_BUF_ENABLED 1U | 161 | #define NVGPU_FB_MMU_FAULT_BUF_ENABLED 1U |
163 | 162 | ||
163 | /* Parameters for init_elcg_mode/init_blcg_mode */ | ||
164 | enum { | ||
165 | ELCG_RUN, /* clk always run, i.e. disable elcg */ | ||
166 | ELCG_STOP, /* clk is stopped */ | ||
167 | ELCG_AUTO /* clk will run when non-idle, standard elcg mode */ | ||
168 | }; | ||
169 | |||
170 | enum { | ||
171 | BLCG_RUN, /* clk always run, i.e. disable blcg */ | ||
172 | BLCG_AUTO /* clk will run when non-idle, standard blcg mode */ | ||
173 | }; | ||
174 | |||
164 | struct gpu_ops { | 175 | struct gpu_ops { |
165 | struct { | 176 | struct { |
166 | int (*determine_L2_size_bytes)(struct gk20a *gk20a); | 177 | int (*determine_L2_size_bytes)(struct gk20a *gk20a); |
@@ -425,7 +436,6 @@ struct gpu_ops { | |||
425 | struct nvgpu_mem *mem, u64 gpu_va); | 436 | struct nvgpu_mem *mem, u64 gpu_va); |
426 | void (*set_preemption_buffer_va)(struct gk20a *g, | 437 | void (*set_preemption_buffer_va)(struct gk20a *g, |
427 | struct nvgpu_mem *mem, u64 gpu_va); | 438 | struct nvgpu_mem *mem, u64 gpu_va); |
428 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); | ||
429 | void (*load_tpc_mask)(struct gk20a *g); | 439 | void (*load_tpc_mask)(struct gk20a *g); |
430 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); | 440 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); |
431 | int (*trigger_suspend)(struct gk20a *g); | 441 | int (*trigger_suspend)(struct gk20a *g); |
@@ -979,6 +989,8 @@ struct gpu_ops { | |||
979 | } pramin; | 989 | } pramin; |
980 | struct { | 990 | struct { |
981 | int (*init_therm_setup_hw)(struct gk20a *g); | 991 | int (*init_therm_setup_hw)(struct gk20a *g); |
992 | void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); | ||
993 | void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine); | ||
982 | int (*elcg_init_idle_filters)(struct gk20a *g); | 994 | int (*elcg_init_idle_filters)(struct gk20a *g); |
983 | #ifdef CONFIG_DEBUG_FS | 995 | #ifdef CONFIG_DEBUG_FS |
984 | void (*therm_debugfs_init)(struct gk20a *g); | 996 | void (*therm_debugfs_init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 5539b801..bb54e00e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -61,7 +61,6 @@ | |||
61 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 61 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
62 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 62 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
63 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | 63 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> |
64 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> | ||
65 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> | 64 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> |
66 | 65 | ||
67 | #define BLK_SIZE (256) | 66 | #define BLK_SIZE (256) |
@@ -4116,72 +4115,6 @@ int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | |||
4116 | gr_gk20a_add_zbc(g, gr, zbc_val)); | 4115 | gr_gk20a_add_zbc(g, gr, zbc_val)); |
4117 | } | 4116 | } |
4118 | 4117 | ||
4119 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | ||
4120 | { | ||
4121 | u32 gate_ctrl; | ||
4122 | |||
4123 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
4124 | return; | ||
4125 | |||
4126 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | ||
4127 | |||
4128 | switch (mode) { | ||
4129 | case BLCG_RUN: | ||
4130 | gate_ctrl = set_field(gate_ctrl, | ||
4131 | therm_gate_ctrl_blk_clk_m(), | ||
4132 | therm_gate_ctrl_blk_clk_run_f()); | ||
4133 | break; | ||
4134 | case BLCG_AUTO: | ||
4135 | gate_ctrl = set_field(gate_ctrl, | ||
4136 | therm_gate_ctrl_blk_clk_m(), | ||
4137 | therm_gate_ctrl_blk_clk_auto_f()); | ||
4138 | break; | ||
4139 | default: | ||
4140 | nvgpu_err(g, | ||
4141 | "invalid blcg mode %d", mode); | ||
4142 | return; | ||
4143 | } | ||
4144 | |||
4145 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | ||
4146 | } | ||
4147 | |||
4148 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | ||
4149 | { | ||
4150 | u32 gate_ctrl; | ||
4151 | |||
4152 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | ||
4153 | |||
4154 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) | ||
4155 | return; | ||
4156 | |||
4157 | switch (mode) { | ||
4158 | case ELCG_RUN: | ||
4159 | gate_ctrl = set_field(gate_ctrl, | ||
4160 | therm_gate_ctrl_eng_clk_m(), | ||
4161 | therm_gate_ctrl_eng_clk_run_f()); | ||
4162 | gate_ctrl = set_field(gate_ctrl, | ||
4163 | therm_gate_ctrl_eng_pwr_m(), | ||
4164 | /* set elpg to auto to meet hw expectation */ | ||
4165 | therm_gate_ctrl_eng_pwr_auto_f()); | ||
4166 | break; | ||
4167 | case ELCG_STOP: | ||
4168 | gate_ctrl = set_field(gate_ctrl, | ||
4169 | therm_gate_ctrl_eng_clk_m(), | ||
4170 | therm_gate_ctrl_eng_clk_stop_f()); | ||
4171 | break; | ||
4172 | case ELCG_AUTO: | ||
4173 | gate_ctrl = set_field(gate_ctrl, | ||
4174 | therm_gate_ctrl_eng_clk_m(), | ||
4175 | therm_gate_ctrl_eng_clk_auto_f()); | ||
4176 | break; | ||
4177 | default: | ||
4178 | nvgpu_err(g, | ||
4179 | "invalid elcg mode %d", mode); | ||
4180 | } | ||
4181 | |||
4182 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | ||
4183 | } | ||
4184 | |||
4185 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) | 4118 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) |
4186 | { | 4119 | { |
4187 | u32 engine_idx; | 4120 | u32 engine_idx; |
@@ -4196,10 +4129,10 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) | |||
4196 | /* gr_engine supports both BLCG and ELCG */ | 4129 | /* gr_engine supports both BLCG and ELCG */ |
4197 | if ((cgmode == BLCG_MODE) && | 4130 | if ((cgmode == BLCG_MODE) && |
4198 | (engine_info->engine_enum == ENGINE_GR_GK20A)) { | 4131 | (engine_info->engine_enum == ENGINE_GR_GK20A)) { |
4199 | gr_gk20a_init_blcg_mode(g, mode_config, active_engine_id); | 4132 | g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id); |
4200 | break; | 4133 | break; |
4201 | } else if (cgmode == ELCG_MODE) | 4134 | } else if (cgmode == ELCG_MODE) |
4202 | g->ops.gr.init_elcg_mode(g, mode_config, | 4135 | g->ops.therm.init_elcg_mode(g, mode_config, |
4203 | active_engine_id); | 4136 | active_engine_id); |
4204 | else | 4137 | else |
4205 | nvgpu_err(g, "invalid cg mode %d, config %d for " | 4138 | nvgpu_err(g, "invalid cg mode %d, config %d for " |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 2b31b6b6..9c9a3caa 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -126,17 +126,6 @@ enum { | |||
126 | }; | 126 | }; |
127 | 127 | ||
128 | enum { | 128 | enum { |
129 | ELCG_RUN, /* clk always run, i.e. disable elcg */ | ||
130 | ELCG_STOP, /* clk is stopped */ | ||
131 | ELCG_AUTO /* clk will run when non-idle, standard elcg mode */ | ||
132 | }; | ||
133 | |||
134 | enum { | ||
135 | BLCG_RUN, /* clk always run, i.e. disable blcg */ | ||
136 | BLCG_AUTO /* clk will run when non-idle, standard blcg mode */ | ||
137 | }; | ||
138 | |||
139 | enum { | ||
140 | NVGPU_EVENT_ID_BPT_INT = 0, | 129 | NVGPU_EVENT_ID_BPT_INT = 0, |
141 | NVGPU_EVENT_ID_BPT_PAUSE, | 130 | NVGPU_EVENT_ID_BPT_PAUSE, |
142 | NVGPU_EVENT_ID_BLOCKING_SYNC, | 131 | NVGPU_EVENT_ID_BLOCKING_SYNC, |
@@ -609,9 +598,6 @@ int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, | |||
609 | struct nvgpu_mem *inst_block); | 598 | struct nvgpu_mem *inst_block); |
610 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | 599 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); |
611 | 600 | ||
612 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | ||
613 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); | ||
614 | |||
615 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); | 601 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); |
616 | 602 | ||
617 | /* sm */ | 603 | /* sm */ |
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c deleted file mode 100644 index b4a81aed..00000000 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c +++ /dev/null | |||
@@ -1,111 +0,0 @@ | |||
1 | /* | ||
2 | * GK20A Therm | ||
3 | * | ||
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/enabled.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/utils.h> | ||
28 | |||
29 | #include "gk20a.h" | ||
30 | |||
31 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | ||
32 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> | ||
33 | |||
34 | static int gk20a_init_therm_reset_enable_hw(struct gk20a *g) | ||
35 | { | ||
36 | return 0; | ||
37 | } | ||
38 | |||
39 | static int gk20a_init_therm_setup_sw(struct gk20a *g) | ||
40 | { | ||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | int gk20a_init_therm_support(struct gk20a *g) | ||
45 | { | ||
46 | u32 err; | ||
47 | |||
48 | nvgpu_log_fn(g, " "); | ||
49 | |||
50 | err = gk20a_init_therm_reset_enable_hw(g); | ||
51 | if (err) | ||
52 | return err; | ||
53 | |||
54 | err = gk20a_init_therm_setup_sw(g); | ||
55 | if (err) | ||
56 | return err; | ||
57 | |||
58 | if (g->ops.therm.init_therm_setup_hw) | ||
59 | err = g->ops.therm.init_therm_setup_hw(g); | ||
60 | if (err) | ||
61 | return err; | ||
62 | |||
63 | #ifdef CONFIG_DEBUG_FS | ||
64 | if (g->ops.therm.therm_debugfs_init) | ||
65 | g->ops.therm.therm_debugfs_init(g); | ||
66 | #endif | ||
67 | |||
68 | return err; | ||
69 | } | ||
70 | |||
71 | int gk20a_elcg_init_idle_filters(struct gk20a *g) | ||
72 | { | ||
73 | u32 gate_ctrl, idle_filter; | ||
74 | u32 engine_id; | ||
75 | u32 active_engine_id = 0; | ||
76 | struct fifo_gk20a *f = &g->fifo; | ||
77 | |||
78 | nvgpu_log_fn(g, " "); | ||
79 | |||
80 | for (engine_id = 0; engine_id < f->num_engines; engine_id++) { | ||
81 | active_engine_id = f->active_engines_list[engine_id]; | ||
82 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); | ||
83 | |||
84 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
85 | gate_ctrl = set_field(gate_ctrl, | ||
86 | therm_gate_ctrl_eng_delay_after_m(), | ||
87 | therm_gate_ctrl_eng_delay_after_f(4)); | ||
88 | } | ||
89 | |||
90 | /* 2 * (1 << 9) = 1024 clks */ | ||
91 | gate_ctrl = set_field(gate_ctrl, | ||
92 | therm_gate_ctrl_eng_idle_filt_exp_m(), | ||
93 | therm_gate_ctrl_eng_idle_filt_exp_f(9)); | ||
94 | gate_ctrl = set_field(gate_ctrl, | ||
95 | therm_gate_ctrl_eng_idle_filt_mant_m(), | ||
96 | therm_gate_ctrl_eng_idle_filt_mant_f(2)); | ||
97 | gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); | ||
98 | } | ||
99 | |||
100 | /* default fecs_idle_filter to 0 */ | ||
101 | idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); | ||
102 | idle_filter &= ~therm_fecs_idle_filter_value_m(); | ||
103 | gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); | ||
104 | /* default hubmmu_idle_filter to 0 */ | ||
105 | idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); | ||
106 | idle_filter &= ~therm_hubmmu_idle_filter_value_m(); | ||
107 | gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); | ||
108 | |||
109 | nvgpu_log_fn(g, "done"); | ||
110 | return 0; | ||
111 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h b/drivers/gpu/nvgpu/gk20a/therm_gk20a.h deleted file mode 100644 index 303c28f4..00000000 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef THERM_GK20A_H | ||
23 | #define THERM_GK20A_H | ||
24 | |||
25 | struct gpu_ops; | ||
26 | struct gk20a; | ||
27 | |||
28 | int gk20a_elcg_init_idle_filters(struct gk20a *g); | ||
29 | |||
30 | int gk20a_init_therm_support(struct gk20a *g); | ||
31 | #endif /* THERM_GK20A_H */ | ||