gpu: nvgpu: add handling for ctxsw_intr0

ctxsw_intr0 is triggered by ucode even if it
is not enabled by driver. Add handling
for processing ctxsw_intr0. fecs mailbox(6)
is used to report fecs/gpccs misc error codes.
Also dump falcon stats for unhandled fecs intr.

Bug 2361571
Bug 200472922

Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966984
(cherry picked from commit 2c379cad0f6a01d07102898b362735a574f3aea8
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/1979745
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 13 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3a166e06..8d65f90a 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5304,10 +5304,18 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
                 nvgpu_err(g, "fecs watchdog triggered for channel %u, "
                                 "cannot ctxsw anymore !!", isr_data->chid);
                 gk20a_fecs_dump_falcon_stats(g);
+        } else if ((gr_fecs_intr &
+                gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
+                u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
+
+                nvgpu_err(g, "ctxsw intr0 set by ucode, error_code: 0x%08x",
+                          mailbox_value);
+                ret = -1;
         } else {
                 nvgpu_err(g,
-                        "fecs error interrupt 0x%08x for channel %u",
-                        gr_fecs_intr, isr_data->chid);
+                        "unhandled fecs error interrupt 0x%08x for channel %u",
+                        gr_fecs_intr, ch->chid);
+                gk20a_fecs_dump_falcon_stats(g);
         }
 
         gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index c4ce49af..25850104 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -66,6 +66,9 @@
 #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA       (1 << 1)
 #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP      (1 << 2)
 
+#define CTXSW_INTR0                             BIT32(0)
+#define CTXSW_INTR1                             BIT32(1)
+
 struct tsg_gk20a;
 struct channel_gk20a;
 struct nvgpu_warpstate;