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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-25 16:03:38 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-05-12 19:09:05 -0400
commit888fbbda21af9ed9b47527cdc0b853c4397005d0 (patch)
treede30fc72733ad7a5e0c8c847cc2e3d5ebab8c9ea /drivers/gpu/nvgpu/gk20a
parent5cbfb69b7ee41507e0ca24c0bc8c7da446784267 (diff)
gpu: nvgpu: Use nvgpu_cond for channel refcount
Use nvgpu_cond for waiting for all channel accesses to finalize before closing a channel, and for signalling for the same event. JIRA NVGPU-14 Change-Id: Ifac14ad9afe5c44d4443b4a4a94a4d0ad2ea7053 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c11
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.h3
2 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index db44d11b..04765eea 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -28,6 +28,7 @@
28#include <nvgpu/bug.h> 28#include <nvgpu/bug.h>
29#include <nvgpu/list.h> 29#include <nvgpu/list.h>
30#include <nvgpu/circ_buf.h> 30#include <nvgpu/circ_buf.h>
31#include <nvgpu/cond.h>
31 32
32#include "gk20a.h" 33#include "gk20a.h"
33#include "debug_gk20a.h" 34#include "debug_gk20a.h"
@@ -385,11 +386,11 @@ void gk20a_channel_free_error_notifiers(struct channel_gk20a *ch)
385 386
386static void gk20a_wait_until_counter_is_N( 387static void gk20a_wait_until_counter_is_N(
387 struct channel_gk20a *ch, atomic_t *counter, int wait_value, 388 struct channel_gk20a *ch, atomic_t *counter, int wait_value,
388 wait_queue_head_t *wq, const char *caller, const char *counter_name) 389 struct nvgpu_cond *c, const char *caller, const char *counter_name)
389{ 390{
390 while (true) { 391 while (true) {
391 if (wait_event_timeout( 392 if (NVGPU_COND_WAIT(
392 *wq, 393 c,
393 atomic_read(counter) == wait_value, 394 atomic_read(counter) == wait_value,
394 msecs_to_jiffies(5000)) > 0) 395 msecs_to_jiffies(5000)) > 0)
395 break; 396 break;
@@ -712,7 +713,7 @@ void _gk20a_channel_put(struct channel_gk20a *ch, const char *caller)
712 gk20a_channel_save_ref_source(ch, channel_gk20a_ref_action_put); 713 gk20a_channel_save_ref_source(ch, channel_gk20a_ref_action_put);
713 trace_gk20a_channel_put(ch->hw_chid, caller); 714 trace_gk20a_channel_put(ch->hw_chid, caller);
714 atomic_dec(&ch->ref_count); 715 atomic_dec(&ch->ref_count);
715 wake_up_all(&ch->ref_count_dec_wq); 716 nvgpu_cond_broadcast(&ch->ref_count_dec_wq);
716 717
717 /* More puts than gets. Channel is probably going to get 718 /* More puts than gets. Channel is probably going to get
718 * stuck. */ 719 * stuck. */
@@ -2624,7 +2625,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid)
2624 nvgpu_spinlock_init(&c->ref_obtain_lock); 2625 nvgpu_spinlock_init(&c->ref_obtain_lock);
2625 atomic_set(&c->ref_count, 0); 2626 atomic_set(&c->ref_count, 0);
2626 c->referenceable = false; 2627 c->referenceable = false;
2627 init_waitqueue_head(&c->ref_count_dec_wq); 2628 nvgpu_cond_init(&c->ref_count_dec_wq);
2628 2629
2629#if GK20A_CHANNEL_REFCOUNT_TRACKING 2630#if GK20A_CHANNEL_REFCOUNT_TRACKING
2630 nvgpu_spinlock_init(&c->ref_actions_lock); 2631 nvgpu_spinlock_init(&c->ref_actions_lock);
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index 3312f8f1..ea77985e 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -24,6 +24,7 @@
24 24
25#include <nvgpu/lock.h> 25#include <nvgpu/lock.h>
26#include <nvgpu/timers.h> 26#include <nvgpu/timers.h>
27#include <nvgpu/cond.h>
27 28
28struct gk20a; 29struct gk20a;
29struct gr_gk20a; 30struct gr_gk20a;
@@ -169,7 +170,7 @@ struct channel_gk20a {
169 struct nvgpu_spinlock ref_obtain_lock; 170 struct nvgpu_spinlock ref_obtain_lock;
170 bool referenceable; 171 bool referenceable;
171 atomic_t ref_count; 172 atomic_t ref_count;
172 wait_queue_head_t ref_count_dec_wq; 173 struct nvgpu_cond ref_count_dec_wq;
173#if GK20A_CHANNEL_REFCOUNT_TRACKING 174#if GK20A_CHANNEL_REFCOUNT_TRACKING
174 /* 175 /*
175 * Ring buffer for most recent refcount gets and puts. Protected by 176 * Ring buffer for most recent refcount gets and puts. Protected by