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authorKevin Huang <kevinh@nvidia.com>2014-07-23 16:52:48 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:10:53 -0400
commit87373abc9598bf5c57f429ea246497d3019a6034 (patch)
treef67b504b391c1c7d1e39183135d983f30525bd9d /drivers/gpu/nvgpu/gk20a
parent92c9a2d06e6caa3c2521f1851b4933d7e90856f2 (diff)
gpu: nvgpu: gm20b: use gpc_mmu to check debug mode
Bug 1534793 Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/441377 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c1
4 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e2b8a12e..b1cd50ea 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -862,7 +862,7 @@ static bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
862 /* channel recovery is only deferred if an sm debugger 862 /* channel recovery is only deferred if an sm debugger
863 is attached and has MMU debug mode is enabled */ 863 is attached and has MMU debug mode is enabled */
864 if (!gk20a_gr_sm_debugger_attached(g) || 864 if (!gk20a_gr_sm_debugger_attached(g) ||
865 !gk20a_mm_mmu_debug_mode_enabled(g)) 865 !g->ops.mm.is_debug_mode_enabled(g))
866 return false; 866 return false;
867 867
868 /* if this fault is fake (due to RC recovery), don't defer recovery */ 868 /* if this fault is fake (due to RC recovery), don't defer recovery */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index b5ef3f0d..77300203 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -239,6 +239,7 @@ struct gpu_ops {
239 u32 num_pages, u32 pgsz_idx); 239 u32 num_pages, u32 pgsz_idx);
240 void (*clear_sparse)(struct vm_gk20a *vm, u64 vaddr, 240 void (*clear_sparse)(struct vm_gk20a *vm, u64 vaddr,
241 u64 size, u32 pgsz_idx); 241 u64 size, u32 pgsz_idx);
242 bool (*is_debug_mode_enabled)(struct gk20a *g);
242 } mm; 243 } mm;
243 struct { 244 struct {
244 int (*prepare_ucode)(struct gk20a *g); 245 int (*prepare_ucode)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3298a383..a2832a9f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5267,7 +5267,7 @@ static int gk20a_gr_lock_down_sm(struct gk20a *g, u32 global_esr_mask)
5267 unsigned long end_jiffies = jiffies + 5267 unsigned long end_jiffies = jiffies +
5268 msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); 5268 msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
5269 u32 delay = GR_IDLE_CHECK_DEFAULT; 5269 u32 delay = GR_IDLE_CHECK_DEFAULT;
5270 bool mmu_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled(g); 5270 bool mmu_debug_mode_enabled = g->ops.mm.is_debug_mode_enabled(g);
5271 u32 dbgr_control0; 5271 u32 dbgr_control0;
5272 5272
5273 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "locking down SM"); 5273 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "locking down SM");
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 93a29b13..92095162 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -3111,5 +3111,6 @@ void gk20a_init_mm(struct gpu_ops *gops)
3111 gops->mm.set_sparse = gk20a_vm_put_sparse; 3111 gops->mm.set_sparse = gk20a_vm_put_sparse;
3112 gops->mm.put_empty = gk20a_vm_put_empty; 3112 gops->mm.put_empty = gk20a_vm_put_empty;
3113 gops->mm.clear_sparse = gk20a_vm_clear_sparse; 3113 gops->mm.clear_sparse = gk20a_vm_clear_sparse;
3114 gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled;
3114} 3115}
3115 3116