diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-09-27 15:35:38 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-08 07:07:16 -0500 |
commit | 86a307871b95a175eb8ecb3033472a112a0720d1 (patch) | |
tree | 7bbc86e5d94bc89e6abfe75b23b7b64633c0cd07 /drivers/gpu/nvgpu/gk20a | |
parent | ec189e454d8fa3defdef1252e149577ce3b6e5b7 (diff) |
gpu: nvgpu: enable pbus intr for si/fpga
Enable pri squash, fecs err and pri_timeout pbus
interrupt for si and fpga platforms only.
Bug 200350539
Change-Id: Id452edf92eac0209d3b43d98b3ff6efd0764e40a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index ba4cfcbe..7f0cfe58 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -36,28 +36,30 @@ | |||
36 | 36 | ||
37 | void gk20a_bus_init_hw(struct gk20a *g) | 37 | void gk20a_bus_init_hw(struct gk20a *g) |
38 | { | 38 | { |
39 | /* enable pri timeout only on silicon */ | 39 | u32 timeout_period, intr_en_mask = 0; |
40 | if (nvgpu_platform_is_silicon(g)) { | 40 | |
41 | if (nvgpu_platform_is_silicon(g)) | ||
42 | timeout_period = g->default_pri_timeout ? | ||
43 | g->default_pri_timeout : 0x186A0; | ||
44 | else | ||
45 | timeout_period = 0x186A0; | ||
46 | |||
47 | if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) { | ||
48 | intr_en_mask = bus_intr_en_0_pri_squash_m() | | ||
49 | bus_intr_en_0_pri_fecserr_m() | | ||
50 | bus_intr_en_0_pri_timeout_m(); | ||
41 | gk20a_writel(g, | 51 | gk20a_writel(g, |
42 | timer_pri_timeout_r(), | 52 | timer_pri_timeout_r(), |
43 | timer_pri_timeout_period_f( | 53 | timer_pri_timeout_period_f(timeout_period) | |
44 | g->default_pri_timeout ? | ||
45 | g->default_pri_timeout : 0x186A0) | | ||
46 | timer_pri_timeout_en_en_enabled_f()); | 54 | timer_pri_timeout_en_en_enabled_f()); |
55 | |||
47 | } else { | 56 | } else { |
48 | gk20a_writel(g, | 57 | gk20a_writel(g, |
49 | timer_pri_timeout_r(), | 58 | timer_pri_timeout_r(), |
50 | timer_pri_timeout_period_f(0x186A0) | | 59 | timer_pri_timeout_period_f(timeout_period) | |
51 | timer_pri_timeout_en_en_disabled_f()); | 60 | timer_pri_timeout_en_en_disabled_f()); |
52 | } | 61 | } |
53 | 62 | gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask); | |
54 | if (!nvgpu_platform_is_silicon(g)) | ||
55 | gk20a_writel(g, bus_intr_en_0_r(), 0x0); | ||
56 | else | ||
57 | gk20a_writel(g, bus_intr_en_0_r(), | ||
58 | bus_intr_en_0_pri_squash_m() | | ||
59 | bus_intr_en_0_pri_fecserr_m() | | ||
60 | bus_intr_en_0_pri_timeout_m()); | ||
61 | } | 63 | } |
62 | 64 | ||
63 | void gk20a_bus_isr(struct gk20a *g) | 65 | void gk20a_bus_isr(struct gk20a *g) |