diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-01-31 10:09:21 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-08 00:53:44 -0500 |
commit | 8522004c00264646feeb30ede3214f46ddbea04d (patch) | |
tree | 920c82db4d0517111269a2b50580734bb323dab3 /drivers/gpu/nvgpu/gk20a | |
parent | 02190c7597d3b1a04ebcbc746b41f949ab699a18 (diff) |
gpu: nvgpu: Falcon-controller interface update
Moved falcon-controller common interface code
from pmu_common.h to flcnif_cmn.h file.
Interfaces are common for falcons irrespective
of F/W on falcon controllers
Jira NVGPU-19
Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_common.h | 135 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 17 |
3 files changed, 3 insertions, 153 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index def7bbea..d4af6bdb 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -14,7 +14,7 @@ | |||
14 | #ifndef __PMU_API_H__ | 14 | #ifndef __PMU_API_H__ |
15 | #define __PMU_API_H__ | 15 | #define __PMU_API_H__ |
16 | 16 | ||
17 | #include "pmu_common.h" | 17 | #include <nvgpu/flcnif_cmn.h> |
18 | #include "pmuif/gpmuif_pg_rppg.h" | 18 | #include "pmuif/gpmuif_pg_rppg.h" |
19 | 19 | ||
20 | /* PMU Command/Message Interfaces for Adaptive Power */ | 20 | /* PMU Command/Message Interfaces for Adaptive Power */ |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h deleted file mode 100644 index 3b3362c1..00000000 --- a/drivers/gpu/nvgpu/gk20a/pmu_common.h +++ /dev/null | |||
@@ -1,135 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __PMU_COMMON_H__ | ||
15 | #define __PMU_COMMON_H__ | ||
16 | |||
17 | #define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0 | ||
18 | |||
19 | struct falc_u64 { | ||
20 | u32 lo; | ||
21 | u32 hi; | ||
22 | }; | ||
23 | |||
24 | struct falc_dma_addr { | ||
25 | u32 dma_base; | ||
26 | /* | ||
27 | * dma_base1 is 9-bit MSB for FB Base | ||
28 | * address for the transfer in FB after | ||
29 | * address using 49b FB address | ||
30 | */ | ||
31 | u16 dma_base1; | ||
32 | u8 dma_offset; | ||
33 | }; | ||
34 | |||
35 | struct pmu_mem_v0 { | ||
36 | u32 dma_base; | ||
37 | u8 dma_offset; | ||
38 | u8 dma_idx; | ||
39 | }; | ||
40 | |||
41 | struct pmu_mem_v1 { | ||
42 | u32 dma_base; | ||
43 | u8 dma_offset; | ||
44 | u8 dma_idx; | ||
45 | u16 fb_size; | ||
46 | }; | ||
47 | |||
48 | struct pmu_mem_v2 { | ||
49 | struct falc_dma_addr dma_addr; | ||
50 | u8 dma_idx; | ||
51 | u16 fb_size; | ||
52 | }; | ||
53 | |||
54 | struct pmu_mem_desc_v0 { | ||
55 | /*! | ||
56 | * Start address of memory surface that is being communicated to the falcon. | ||
57 | */ | ||
58 | struct falc_u64 dma_addr; | ||
59 | /*! | ||
60 | * Max allowed DMA transfer size (size of the memory surface). Accesses past | ||
61 | * this point may result in page faults and/or memory corruptions. | ||
62 | */ | ||
63 | u16 dma_sizemax; | ||
64 | /*! | ||
65 | * DMA channel index to be used when accessing this surface. | ||
66 | */ | ||
67 | u8 dma_idx; | ||
68 | }; | ||
69 | |||
70 | struct pmu_dmem { | ||
71 | u16 size; | ||
72 | u32 offset; | ||
73 | }; | ||
74 | |||
75 | struct flcn_u64 { | ||
76 | u32 lo; | ||
77 | u32 hi; | ||
78 | }; | ||
79 | |||
80 | #define nv_flcn_u64 flcn_u64 | ||
81 | |||
82 | struct flcn_mem_desc_v0 { | ||
83 | struct flcn_u64 address; | ||
84 | u32 params; | ||
85 | }; | ||
86 | |||
87 | #define nv_flcn_mem_desc flcn_mem_desc_v0 | ||
88 | |||
89 | struct pmu_allocation_v0 { | ||
90 | u8 pad[3]; | ||
91 | u8 fb_mem_use; | ||
92 | struct { | ||
93 | struct pmu_dmem dmem; | ||
94 | struct pmu_mem_v0 fb; | ||
95 | } alloc; | ||
96 | }; | ||
97 | |||
98 | struct pmu_allocation_v1 { | ||
99 | struct { | ||
100 | struct pmu_dmem dmem; | ||
101 | struct pmu_mem_v1 fb; | ||
102 | } alloc; | ||
103 | }; | ||
104 | |||
105 | struct pmu_allocation_v2 { | ||
106 | struct { | ||
107 | struct pmu_dmem dmem; | ||
108 | struct pmu_mem_desc_v0 fb; | ||
109 | } alloc; | ||
110 | }; | ||
111 | |||
112 | struct pmu_allocation_v3 { | ||
113 | struct { | ||
114 | struct pmu_dmem dmem; | ||
115 | struct flcn_mem_desc_v0 fb; | ||
116 | } alloc; | ||
117 | }; | ||
118 | |||
119 | #define nv_pmu_allocation pmu_allocation_v3 | ||
120 | |||
121 | struct pmu_hdr { | ||
122 | u8 unit_id; | ||
123 | u8 size; | ||
124 | u8 ctrl_flags; | ||
125 | u8 seq_id; | ||
126 | }; | ||
127 | |||
128 | #define nv_pmu_hdr pmu_hdr | ||
129 | typedef u8 flcn_status; | ||
130 | |||
131 | #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) | ||
132 | |||
133 | #define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) | ||
134 | |||
135 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 84377d0b..dc23005e 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -23,7 +23,7 @@ | |||
23 | 23 | ||
24 | #include <linux/version.h> | 24 | #include <linux/version.h> |
25 | #include "pmu_api.h" | 25 | #include "pmu_api.h" |
26 | #include "pmu_common.h" | 26 | #include <nvgpu/flcnif_cmn.h> |
27 | #include "pmuif/nvgpu_gpmu_cmdif.h" | 27 | #include "pmuif/nvgpu_gpmu_cmdif.h" |
28 | 28 | ||
29 | /* defined by pmu hw spec */ | 29 | /* defined by pmu hw spec */ |
@@ -124,21 +124,6 @@ struct pmu_ucode_desc_v1 { | |||
124 | u32 compressed; | 124 | u32 compressed; |
125 | }; | 125 | }; |
126 | 126 | ||
127 | #define PMU_DMEM_ALLOC_ALIGNMENT (4) | ||
128 | #define PMU_DMEM_ALIGNMENT (4) | ||
129 | |||
130 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) | ||
131 | |||
132 | #define PMU_CMD_FLAGS_STATUS BIT(0) | ||
133 | #define PMU_CMD_FLAGS_INTR BIT(1) | ||
134 | #define PMU_CMD_FLAGS_EVENT BIT(2) | ||
135 | #define PMU_CMD_FLAGS_WATERMARK BIT(3) | ||
136 | |||
137 | #define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) | ||
138 | #define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) | ||
139 | |||
140 | |||
141 | |||
142 | /***************************** ACR ERROR CODES ******************************/ | 127 | /***************************** ACR ERROR CODES ******************************/ |
143 | /*! | 128 | /*! |
144 | * Error codes used in PMU-ACR Task | 129 | * Error codes used in PMU-ACR Task |