gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses

Added new defines for following litter values:
GPU_LIT_SMPC_PRI_BASE
GPU_LIT_SMPC_PRI_SHARED_BASE
GPU_LIT_SMPC_PRI_UNIQUE_BASE9
GPU_LIT_SMPC_PRI_STRIDE

Calculate offsets for ctx operations considering
sm per tpc. Following functions are modified for this:
gr_gk20a_get_ctx_buffer_offsets
gr_gk20a_get_pm_ctx_buffer_offsets
__gr_gk20a_exec_ctx_ops

Bug 200337994

Change-Id: I3a4ca470a4107d3078b708f38601762626ce1bf1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 13 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index dbf36f5c..8dabee63 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -129,6 +129,10 @@ enum gk20a_cbc_op {
 #define GPU_LIT_FBPA_BASE       24
 #define GPU_LIT_FBPA_SHARED_BASE 25
 #define GPU_LIT_SM_PRI_STRIDE   26
+#define GPU_LIT_SMPC_PRI_BASE           27
+#define GPU_LIT_SMPC_PRI_SHARED_BASE    28
+#define GPU_LIT_SMPC_PRI_UNIQUE_BASE    29
+#define GPU_LIT_SMPC_PRI_STRIDE         30
 
 #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
 
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 4c4f8253..679b8492 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6363,7 +6363,9 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
         u32 num_registers = 0;
         int err = 0;
         struct gr_gk20a *gr = &g->gr;
-        u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
+        u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+        u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count *
+                                        sm_per_tpc;
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
@@ -6441,7 +6443,9 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g,
         u32 num_registers = 0;
         int err = 0;
         struct gr_gk20a *gr = &g->gr;
-        u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
+        u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+        u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count *
+                                        sm_per_tpc;
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
@@ -7719,7 +7723,9 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
         struct nvgpu_mem *current_mem = NULL;
         u32 i, j, offset, v;
         struct gr_gk20a *gr = &g->gr;
-        u32 max_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
+        u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+        u32 max_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count *
+                                sm_per_tpc;
         u32 *offsets = NULL;
         u32 *offset_addrs = NULL;
         u32 ctx_op_nr, num_ctx_ops[2] = {num_ctx_wr_ops, num_ctx_rd_ops};