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author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-09-01 06:06:09 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-30 12:30:02 -0400 |
commit | 7f3f9268c0657866716653409cde78fa00c4df61 (patch) | |
tree | 3db52d5ed1e7382d08d10330a064245e40a7e56b /drivers/gpu/nvgpu/gk20a | |
parent | f4be6c43734c29f2be022d43504fb2308b8dbac1 (diff) |
gpu: nvgpu: update PMU version & params
- Update PMU version to support r370
- flcn_bl_dmem_desc_v1 params update to
support PMU bootloader
- PMU_UNIT_CLK value update
JIRA DNVGPU-116
Change-Id: Ic4096e4a5ea55ca6b7c72670061e55b4719e0895
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1212834
(cherry picked from commit 32257231733303b0859230719f3857ad2d9d8820)
Reviewed-on: http://git-master/r/1227289
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index fd27ab5c..78a37436 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -38,7 +38,7 @@ | |||
38 | #define APP_VERSION_NC_1 20313802 | 38 | #define APP_VERSION_NC_1 20313802 |
39 | #define APP_VERSION_NC_0 20360931 | 39 | #define APP_VERSION_NC_0 20360931 |
40 | #define APP_VERSION_GM206 20652057 | 40 | #define APP_VERSION_GM206 20652057 |
41 | #define APP_VERSION_NV_GPU 20660622 | 41 | #define APP_VERSION_NV_GPU 21082352 |
42 | #define APP_VERSION_NV_GPU_1 20799797 | 42 | #define APP_VERSION_NV_GPU_1 20799797 |
43 | #define APP_VERSION_GM20B_5 20490253 | 43 | #define APP_VERSION_GM20B_5 20490253 |
44 | #define APP_VERSION_GM20B_4 19008461 | 44 | #define APP_VERSION_GM20B_4 19008461 |
@@ -178,7 +178,7 @@ struct pmu_ucode_desc_v1 { | |||
178 | #define PMU_UNIT_PERF (0x13) | 178 | #define PMU_UNIT_PERF (0x13) |
179 | #define PMU_UNIT_RC (0x1F) | 179 | #define PMU_UNIT_RC (0x1F) |
180 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) | 180 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) |
181 | #define PMU_UNIT_CLK (0x1C) | 181 | #define PMU_UNIT_CLK (0x0D) |
182 | 182 | ||
183 | #define PMU_UNIT_END (0x23) | 183 | #define PMU_UNIT_END (0x23) |
184 | 184 | ||
@@ -255,10 +255,11 @@ struct pmu_init_msg_pmu_v2 { | |||
255 | u8 dummy[18]; | 255 | u8 dummy[18]; |
256 | }; | 256 | }; |
257 | 257 | ||
258 | #define PMU_QUEUE_COUNT_FOR_V3 3 | ||
258 | struct pmu_init_msg_pmu_v3 { | 259 | struct pmu_init_msg_pmu_v3 { |
259 | u8 msg_type; | 260 | u8 msg_type; |
260 | u8 queue_index[PMU_QUEUE_COUNT]; | 261 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; |
261 | u16 queue_size[PMU_QUEUE_COUNT]; | 262 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; |
262 | u16 queue_offset; | 263 | u16 queue_offset; |
263 | 264 | ||
264 | u16 sw_managed_area_offset; | 265 | u16 sw_managed_area_offset; |