gpu: nvgpu: use HAL for chiplet offset

We currently use hard coded values of NV_PERF_PMMGPC_CHIPLET_OFFSET and
NV_PMM_FBP_STRIDE which are incorrect for Volta

Add new GR HAL get_pmm_per_chiplet_offset() to get correct value per-chip
Set gr_gm20b_get_pmm_per_chiplet_offset() for older chips
Set gr_gv11b_get_pmm_per_chiplet_offset() for Volta

Use HAL instead of hard coded values wherever required

Bug 200398811
Jira NVGPU-556

Change-Id: I947e7febd4f84fae740a1bc74f99d72e1df523aa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690028
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 5 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index edc1c5ff..c2a8d6ce 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -470,6 +470,7 @@ struct gpu_ops {
                                            u32 addr,
                                            u32 *priv_addr_table,
                                            u32 *num_registers);
+                u32 (*get_pmm_per_chiplet_offset)(void);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 04d00e55..e4344b9f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -63,9 +63,7 @@
 #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
 
 #define BLK_SIZE (256)
-#define NV_PMM_FBP_STRIDE       0x1000
 #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200
-#define NV_PERF_PMMGPC_CHIPLET_OFFSET   0x1000
 #define NV_PERF_PMMGPCROUTER_STRIDE     0x0200
 #define NV_PCFG_BASE            0x00088000
 #define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE       0x0020
@@ -7563,7 +7561,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
                                         count, offset, max_cnt, base, ~0))
                         return -EINVAL;
 
-                base = (NV_PERF_PMMGPC_CHIPLET_OFFSET * gpc_num);
+                base = (g->ops.gr.get_pmm_per_chiplet_offset() * gpc_num);
                 if (add_ctxsw_buffer_map_entries(map,
                                         &g->gr.ctx_vars.ctxsw_regs.perf_gpc,
                                         count, offset, max_cnt, base, ~0))
@@ -7703,7 +7701,9 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g)
                                         &g->gr.ctx_vars.ctxsw_regs.fbp,
                                         &count, &offset,
                                         hwpm_ctxsw_reg_count_max, 0,
-                                        g->gr.num_fbps, NV_PMM_FBP_STRIDE, ~0))
+                                        g->gr.num_fbps,
+                                        g->ops.gr.get_pmm_per_chiplet_offset(),
+                                        ~0))
                 goto cleanup;
 
         /* Add entries from _LIST_nv_perf_fbprouter_ctx_regs */