diff options
author | Vijayakumar <vsubbu@nvidia.com> | 2014-09-30 10:49:44 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:52 -0400 |
commit | 748475df20bbe6843bdf4fbc02384dc5aa28866e (patch) | |
tree | 700012cf758d6731017b8b23153abae4311bf065 /drivers/gpu/nvgpu/gk20a | |
parent | 4739499f07b29282ee1031d08adaa76c238da2a6 (diff) |
gpu: nvgpu: gm20b: Support secure FECS recovery
When falcons are secured use PMU commands to reload
FECS firmware.
Bug 200042729
Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/552544
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 90 |
3 files changed, 106 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 20afd2bd..5669e1c5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -307,6 +307,10 @@ struct gpu_ops { | |||
307 | int (*prepare_ucode)(struct gk20a *g); | 307 | int (*prepare_ucode)(struct gk20a *g); |
308 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); | 308 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); |
309 | int (*pmu_setup_elpg)(struct gk20a *g); | 309 | int (*pmu_setup_elpg)(struct gk20a *g); |
310 | int (*init_wpr_region)(struct gk20a *g); | ||
311 | bool lspmuwprinitdone; | ||
312 | bool fecsbootstrapdone; | ||
313 | u32 fecsrecoveryinprogress; | ||
310 | } pmu; | 314 | } pmu; |
311 | struct { | 315 | struct { |
312 | int (*init_clk_support)(struct gk20a *g); | 316 | int (*init_clk_support)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index e60de70b..0580f19d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2262,6 +2262,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2262 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; | 2262 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; |
2263 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; | 2263 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; |
2264 | gops->pmu.pmu_setup_elpg = NULL; | 2264 | gops->pmu.pmu_setup_elpg = NULL; |
2265 | gops->pmu.init_wpr_region = NULL; | ||
2265 | } | 2266 | } |
2266 | 2267 | ||
2267 | int gk20a_init_pmu_support(struct gk20a *g) | 2268 | int gk20a_init_pmu_support(struct gk20a *g) |
@@ -2749,7 +2750,7 @@ static int pmu_response_handle(struct pmu_gk20a *pmu, | |||
2749 | return 0; | 2750 | return 0; |
2750 | } | 2751 | } |
2751 | 2752 | ||
2752 | static int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, | 2753 | int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, |
2753 | u32 *var, u32 val); | 2754 | u32 *var, u32 val); |
2754 | 2755 | ||
2755 | static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, | 2756 | static void pmu_handle_zbc_msg(struct gk20a *g, struct pmu_msg *msg, |
@@ -2902,10 +2903,14 @@ static int pmu_process_message(struct pmu_gk20a *pmu) | |||
2902 | { | 2903 | { |
2903 | struct pmu_msg msg; | 2904 | struct pmu_msg msg; |
2904 | int status; | 2905 | int status; |
2906 | struct gk20a *g = gk20a_from_pmu(pmu); | ||
2905 | 2907 | ||
2906 | if (unlikely(!pmu->pmu_ready)) { | 2908 | if (unlikely(!pmu->pmu_ready)) { |
2907 | pmu_process_init_msg(pmu, &msg); | 2909 | pmu_process_init_msg(pmu, &msg); |
2910 | if (g->ops.pmu.init_wpr_region != NULL) | ||
2911 | g->ops.pmu.init_wpr_region(g); | ||
2908 | pmu_init_perfmon(pmu); | 2912 | pmu_init_perfmon(pmu); |
2913 | |||
2909 | return 0; | 2914 | return 0; |
2910 | } | 2915 | } |
2911 | 2916 | ||
@@ -2930,7 +2935,7 @@ static int pmu_process_message(struct pmu_gk20a *pmu) | |||
2930 | return 0; | 2935 | return 0; |
2931 | } | 2936 | } |
2932 | 2937 | ||
2933 | static int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, | 2938 | int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, |
2934 | u32 *var, u32 val) | 2939 | u32 *var, u32 val) |
2935 | { | 2940 | { |
2936 | struct gk20a *g = gk20a_from_pmu(pmu); | 2941 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -3166,10 +3171,11 @@ void gk20a_pmu_isr(struct gk20a *g) | |||
3166 | mask = gk20a_readl(g, pwr_falcon_irqmask_r()) & | 3171 | mask = gk20a_readl(g, pwr_falcon_irqmask_r()) & |
3167 | gk20a_readl(g, pwr_falcon_irqdest_r()); | 3172 | gk20a_readl(g, pwr_falcon_irqdest_r()); |
3168 | 3173 | ||
3169 | intr = gk20a_readl(g, pwr_falcon_irqstat_r()) & mask; | 3174 | intr = gk20a_readl(g, pwr_falcon_irqstat_r()); |
3170 | 3175 | ||
3171 | gk20a_dbg_pmu("received falcon interrupt: 0x%08x", intr); | 3176 | gk20a_dbg_pmu("received falcon interrupt: 0x%08x", intr); |
3172 | 3177 | ||
3178 | intr = gk20a_readl(g, pwr_falcon_irqstat_r()) & mask; | ||
3173 | if (!intr || pmu->pmu_state == PMU_STATE_OFF) { | 3179 | if (!intr || pmu->pmu_state == PMU_STATE_OFF) { |
3174 | gk20a_writel(g, pwr_falcon_irqsclr_r(), intr); | 3180 | gk20a_writel(g, pwr_falcon_irqsclr_r(), intr); |
3175 | mutex_unlock(&pmu->isr_mutex); | 3181 | mutex_unlock(&pmu->isr_mutex); |
@@ -3631,6 +3637,10 @@ int gk20a_pmu_destroy(struct gk20a *g) | |||
3631 | pmu->pmu_ready = false; | 3637 | pmu->pmu_ready = false; |
3632 | pmu->perfmon_ready = false; | 3638 | pmu->perfmon_ready = false; |
3633 | pmu->zbc_ready = false; | 3639 | pmu->zbc_ready = false; |
3640 | g->ops.pmu.lspmuwprinitdone = false; | ||
3641 | g->ops.pmu.fecsbootstrapdone = false; | ||
3642 | g->ops.pmu.fecsrecoveryinprogress = 0; | ||
3643 | |||
3634 | 3644 | ||
3635 | gk20a_dbg_fn("done"); | 3645 | gk20a_dbg_fn("done"); |
3636 | return 0; | 3646 | return 0; |
@@ -3738,7 +3748,6 @@ int gk20a_pmu_ap_send_command(struct gk20a *g, | |||
3738 | gk20a_dbg_pmu("cmd post PMU_AP_CMD_ID_INIT"); | 3748 | gk20a_dbg_pmu("cmd post PMU_AP_CMD_ID_INIT"); |
3739 | cmd.cmd.pg.ap_cmd.init.pg_sampling_period_us = | 3749 | cmd.cmd.pg.ap_cmd.init.pg_sampling_period_us = |
3740 | p_ap_cmd->init.pg_sampling_period_us; | 3750 | p_ap_cmd->init.pg_sampling_period_us; |
3741 | p_callback = ap_callback_init_and_enable_ctrl; | ||
3742 | break; | 3751 | break; |
3743 | 3752 | ||
3744 | case PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL: | 3753 | case PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL: |
@@ -3782,7 +3791,7 @@ int gk20a_pmu_ap_send_command(struct gk20a *g, | |||
3782 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 3791 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
3783 | p_callback, pmu, &seq, ~0); | 3792 | p_callback, pmu, &seq, ~0); |
3784 | 3793 | ||
3785 | if (!status) { | 3794 | if (status) { |
3786 | gk20a_dbg_pmu( | 3795 | gk20a_dbg_pmu( |
3787 | "%s: Unable to submit Adaptive Power Command %d\n", | 3796 | "%s: Unable to submit Adaptive Power Command %d\n", |
3788 | __func__, p_ap_cmd->cmn.cmd_id); | 3797 | __func__, p_ap_cmd->cmn.cmd_id); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 6dd1ad3b..823f5484 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -291,7 +291,6 @@ struct pmu_ap { | |||
291 | struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; | 291 | struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; |
292 | }; | 292 | }; |
293 | 293 | ||
294 | |||
295 | enum { | 294 | enum { |
296 | GK20A_PMU_DMAIDX_UCODE = 0, | 295 | GK20A_PMU_DMAIDX_UCODE = 0, |
297 | GK20A_PMU_DMAIDX_VIRT = 1, | 296 | GK20A_PMU_DMAIDX_VIRT = 1, |
@@ -390,7 +389,7 @@ struct pmu_ucode_desc { | |||
390 | #define PMU_UNIT_INIT (0x07) | 389 | #define PMU_UNIT_INIT (0x07) |
391 | #define PMU_UNIT_FBBA (0x08) | 390 | #define PMU_UNIT_FBBA (0x08) |
392 | #define PMU_UNIT_DIDLE (0x09) | 391 | #define PMU_UNIT_DIDLE (0x09) |
393 | #define PMU_UNIT_AVAILABLE3 (0x0A) | 392 | #define PMU_UNIT_ACR (0x0A) |
394 | #define PMU_UNIT_AVAILABLE4 (0x0B) | 393 | #define PMU_UNIT_AVAILABLE4 (0x0B) |
395 | #define PMU_UNIT_HDCP_MAIN (0x0C) | 394 | #define PMU_UNIT_HDCP_MAIN (0x0C) |
396 | #define PMU_UNIT_HDCP_V (0x0D) | 395 | #define PMU_UNIT_HDCP_V (0x0D) |
@@ -643,6 +642,89 @@ struct pmu_pg_cmd { | |||
643 | }; | 642 | }; |
644 | }; | 643 | }; |
645 | 644 | ||
645 | /* ACR Commands/Message structures */ | ||
646 | |||
647 | enum { | ||
648 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 , | ||
649 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, | ||
650 | }; | ||
651 | |||
652 | /* | ||
653 | * Initializes the WPR region details | ||
654 | */ | ||
655 | struct pmu_acr_cmd_init_wpr_details { | ||
656 | u8 cmd_type; | ||
657 | u32 regionid; | ||
658 | u32 wproffset; | ||
659 | |||
660 | }; | ||
661 | |||
662 | /* | ||
663 | * falcon ID to bootstrap | ||
664 | */ | ||
665 | struct pmu_acr_cmd_bootstrap_falcon { | ||
666 | u8 cmd_type; | ||
667 | u32 flags; | ||
668 | u32 falconid; | ||
669 | }; | ||
670 | |||
671 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 | ||
672 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 | ||
673 | |||
674 | struct pmu_acr_cmd { | ||
675 | union { | ||
676 | u8 cmd_type; | ||
677 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; | ||
678 | struct pmu_acr_cmd_init_wpr_details init_wpr; | ||
679 | }; | ||
680 | }; | ||
681 | |||
682 | /* acr messages */ | ||
683 | |||
684 | /* | ||
685 | * returns the WPR region init information | ||
686 | */ | ||
687 | #define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 | ||
688 | |||
689 | /* | ||
690 | * Returns the Bootstrapped falcon ID to RM | ||
691 | */ | ||
692 | #define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 | ||
693 | |||
694 | /* | ||
695 | * Returns the WPR init status | ||
696 | */ | ||
697 | #define PMU_ACR_SUCCESS 0 | ||
698 | #define PMU_ACR_ERROR 1 | ||
699 | |||
700 | /* | ||
701 | * PMU notifies about bootstrap status of falcon | ||
702 | */ | ||
703 | struct pmu_acr_msg_bootstrap_falcon { | ||
704 | u8 msg_type; | ||
705 | union { | ||
706 | u32 errorcode; | ||
707 | u32 falconid; | ||
708 | }; | ||
709 | }; | ||
710 | |||
711 | struct pmu_acr_msg { | ||
712 | union { | ||
713 | u8 msg_type; | ||
714 | struct pmu_acr_msg_bootstrap_falcon acrmsg; | ||
715 | }; | ||
716 | }; | ||
717 | |||
718 | /***************************** ACR ERROR CODES ******************************/ | ||
719 | /*! | ||
720 | * Error codes used in PMU-ACR Task | ||
721 | * | ||
722 | * LSF_ACR_INVALID_TRANSCFG_SETUP : Indicates that TRANSCFG Setup is not valid | ||
723 | * MAILBOX1 returns the CTXDMA ID of invalid setup | ||
724 | * | ||
725 | */ | ||
726 | #define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001) | ||
727 | |||
646 | /* PERFMON */ | 728 | /* PERFMON */ |
647 | #define PMU_DOMAIN_GROUP_PSTATE 0 | 729 | #define PMU_DOMAIN_GROUP_PSTATE 0 |
648 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | 730 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 |
@@ -770,6 +852,7 @@ struct pmu_cmd { | |||
770 | struct pmu_perfmon_cmd perfmon; | 852 | struct pmu_perfmon_cmd perfmon; |
771 | struct pmu_pg_cmd pg; | 853 | struct pmu_pg_cmd pg; |
772 | struct pmu_zbc_cmd zbc; | 854 | struct pmu_zbc_cmd zbc; |
855 | struct pmu_acr_cmd acr; | ||
773 | } cmd; | 856 | } cmd; |
774 | }; | 857 | }; |
775 | 858 | ||
@@ -780,6 +863,7 @@ struct pmu_msg { | |||
780 | struct pmu_perfmon_msg perfmon; | 863 | struct pmu_perfmon_msg perfmon; |
781 | struct pmu_pg_msg pg; | 864 | struct pmu_pg_msg pg; |
782 | struct pmu_rc_msg rc; | 865 | struct pmu_rc_msg rc; |
866 | struct pmu_acr_msg acr; | ||
783 | } msg; | 867 | } msg; |
784 | }; | 868 | }; |
785 | 869 | ||
@@ -1145,4 +1229,6 @@ int gk20a_pmu_ap_send_command(struct gk20a *g, | |||
1145 | int gk20a_aelpg_init(struct gk20a *g); | 1229 | int gk20a_aelpg_init(struct gk20a *g); |
1146 | int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); | 1230 | int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id); |
1147 | void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable); | 1231 | void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable); |
1232 | int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, | ||
1233 | u32 *var, u32 val); | ||
1148 | #endif /*__PMU_GK20A_H__*/ | 1234 | #endif /*__PMU_GK20A_H__*/ |