diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-04-18 19:18:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-01 19:33:11 -0400 |
commit | 744f7f049867c83ecb2c76681cb80ec789459491 (patch) | |
tree | 15fb1bef19a32921d7c33fb8668e773a6bf62a0d /drivers/gpu/nvgpu/gk20a | |
parent | d61d72bfb51e8ac8375b85dd9125e146ba60fe0e (diff) |
gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size
fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug
Bug 2093809
Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 65750a15..e48af08c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -474,6 +474,7 @@ struct gpu_ops { | |||
474 | u32 num_fbpas, | 474 | u32 num_fbpas, |
475 | u32 *priv_addr_table, | 475 | u32 *priv_addr_table, |
476 | u32 *priv_addr_table_index); | 476 | u32 *priv_addr_table_index); |
477 | u32 (*fecs_ctxsw_mailbox_size)(void); | ||
477 | } gr; | 478 | } gr; |
478 | struct { | 479 | struct { |
479 | void (*init_hw)(struct gk20a *g); | 480 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 51bb2551..d26d8a93 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -155,8 +155,10 @@ void gk20a_fecs_dump_falcon_stats(struct gk20a *g) | |||
155 | gk20a_readl(g, gr_fecs_debug1_r())); | 155 | gk20a_readl(g, gr_fecs_debug1_r())); |
156 | nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x", | 156 | nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x", |
157 | gk20a_readl(g, gr_fecs_debuginfo_r())); | 157 | gk20a_readl(g, gr_fecs_debuginfo_r())); |
158 | nvgpu_err(g, "gr_fecs_ctxsw_status_1_r : 0x%x", | ||
159 | gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); | ||
158 | 160 | ||
159 | for (i = 0; i < gr_fecs_ctxsw_mailbox__size_1_v(); i++) | 161 | for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++) |
160 | nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x", | 162 | nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x", |
161 | i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i))); | 163 | i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i))); |
162 | 164 | ||