gpu: nvgpu: correct calculation of sm_id for .record_sm_error_state

Starting with Volta, one TPC could have more than 1 SMs. So
.record_sm_error_state needs to have sm number as parameter.
Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r.

Let the function return logical sm_id. RM server will need it to nofify
client.

Jira EVLR-2643
Bug 200405202

Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a2b2e53f..49f2a34a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -368,8 +368,8 @@ struct gpu_ops {
                 void (*enable_exceptions)(struct gk20a *g);
                 void (*create_gr_sysfs)(struct gk20a *g);
                 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
-                int (*record_sm_error_state)(struct gk20a *g, u32 gpc,
-                                u32 tpc, struct channel_gk20a *fault_ch);
+                int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc,
+                                u32 sm, struct channel_gk20a *fault_ch);
                 int (*update_sm_error_state)(struct gk20a *g,
                                 struct channel_gk20a *ch, u32 sm_id,
                                 struct nvgpu_gr_sm_error_state *sm_error_state);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 37ac8748..a082cd92 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5608,7 +5608,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                   "sm hww global 0x%08x warp 0x%08x", global_esr, warp_esr);
 
         gr_gk20a_elpg_protected_call(g,
-                g->ops.gr.record_sm_error_state(g, gpc, tpc, fault_ch));
+                g->ops.gr.record_sm_error_state(g, gpc, tpc, sm, fault_ch));
 
         if (g->ops.gr.pre_process_sm_exception) {
                 ret = g->ops.gr.pre_process_sm_exception(g, gpc, tpc, sm,