diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-27 15:26:32 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-27 06:57:00 -0400 |
commit | 69222f2de6cf9a29ee5999d9802d806b6966a7e1 (patch) | |
tree | bae9d6d619ba14953b023e4808278047b8b6afac /drivers/gpu/nvgpu/gk20a | |
parent | f2f68430372d42be0b51b7475d8b8236894d96f5 (diff) |
gpu: nvgpu: add fifo ops for handling pbdma_intr_1
This is needed to handle new pbmda intr_1 in t19x
JIRA GPUT19X-47
Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1329373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 |
3 files changed, 25 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 37e19ef8..69a3e706 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2391,6 +2391,23 @@ unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, | |||
2391 | return rc_type; | 2391 | return rc_type; |
2392 | } | 2392 | } |
2393 | 2393 | ||
2394 | unsigned int gk20a_fifo_handle_pbdma_intr_1(struct gk20a *g, | ||
2395 | u32 pbdma_id, u32 pbdma_intr_1, | ||
2396 | u32 *handled, u32 *error_notifier) | ||
2397 | { | ||
2398 | unsigned int rc_type = RC_TYPE_PBDMA_FAULT; | ||
2399 | |||
2400 | /* | ||
2401 | * all of the interrupts in _intr_1 are "host copy engine" | ||
2402 | * related, which is not supported. For now just make them | ||
2403 | * channel fatal. | ||
2404 | */ | ||
2405 | nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x", | ||
2406 | pbdma_id, pbdma_intr_1); | ||
2407 | *handled |= pbdma_intr_1; | ||
2408 | |||
2409 | return rc_type; | ||
2410 | } | ||
2394 | static u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, | 2411 | static u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, |
2395 | struct fifo_gk20a *f, | 2412 | struct fifo_gk20a *f, |
2396 | u32 pbdma_id) | 2413 | u32 pbdma_id) |
@@ -2413,12 +2430,9 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, | |||
2413 | gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); | 2430 | gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); |
2414 | } | 2431 | } |
2415 | 2432 | ||
2416 | /* all intrs in _intr_1 are "host copy engine" related, | ||
2417 | * which gk20a doesn't have. for now just make them channel fatal. */ | ||
2418 | if (pbdma_intr_1) { | 2433 | if (pbdma_intr_1) { |
2419 | nvgpu_err(g, "channel hce error: pbdma_intr_1(%d): 0x%08x", | 2434 | rc_type = g->ops.fifo.handle_pbdma_intr_1(g, pbdma_id, |
2420 | pbdma_id, pbdma_intr_1); | 2435 | pbdma_intr_1, &handled, &error_notifier); |
2421 | rc_type = RC_TYPE_PBDMA_FAULT; | ||
2422 | gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); | 2436 | gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); |
2423 | } | 2437 | } |
2424 | 2438 | ||
@@ -4116,6 +4130,7 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4116 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | 4130 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; |
4117 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; | 4131 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; |
4118 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; | 4132 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; |
4133 | gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1; | ||
4119 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 4134 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
4120 | gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; | 4135 | gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; |
4121 | gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; | 4136 | gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 1566302f..7e919346 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -390,6 +390,8 @@ void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, | |||
390 | int pbdma_method_index); | 390 | int pbdma_method_index); |
391 | unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, | 391 | unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, |
392 | u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); | 392 | u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); |
393 | unsigned int gk20a_fifo_handle_pbdma_intr_1(struct gk20a *g, u32 pbdma_id, | ||
394 | u32 pbdma_intr_1, u32 *handled, u32 *error_notifier); | ||
393 | 395 | ||
394 | u32 gk20a_fifo_default_timeslice_us(struct gk20a *g); | 396 | u32 gk20a_fifo_default_timeslice_us(struct gk20a *g); |
395 | 397 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ffce1c5e..61d2dd84 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -492,6 +492,9 @@ struct gpu_ops { | |||
492 | unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, | 492 | unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, |
493 | u32 pbdma_id, u32 pbdma_intr_0, | 493 | u32 pbdma_id, u32 pbdma_intr_0, |
494 | u32 *handled, u32 *error_notifier); | 494 | u32 *handled, u32 *error_notifier); |
495 | unsigned int (*handle_pbdma_intr_1)(struct gk20a *g, | ||
496 | u32 pbdma_id, u32 pbdma_intr_1, | ||
497 | u32 *handled, u32 *error_notifier); | ||
495 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 498 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
496 | int (*alloc_syncpt_buf)(struct channel_gk20a *c, | 499 | int (*alloc_syncpt_buf)(struct channel_gk20a *c, |
497 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); | 500 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); |