diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-03 08:12:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-12-26 01:20:08 -0500 |
commit | 66ed536fb5e57ad73ffbaf24f9c02f0655e7d6cc (patch) | |
tree | 6a45dae2f0fa61d5e0173abf3d7a2eb8cd3437e7 /drivers/gpu/nvgpu/gk20a | |
parent | e4e0a32c7cccb3389a6afdbf1199d7104391ac01 (diff) |
gpu: nvgpu: rppg support
Add defines and interface structures used for sending PMU
messages to control RPPG.
JIRA DNVGPU-71
Change-Id: Ibec975f3c976619542d8f088b24271796a03f03c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247487
(cherry picked from commit dd3826abca0a51d473d5d9cb25dc84cada9e7878)
Reviewed-on: http://git-master/r/1270793
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index d256f6d2..2fdd1333 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h | |||
@@ -15,6 +15,7 @@ | |||
15 | #define __PMU_API_H__ | 15 | #define __PMU_API_H__ |
16 | 16 | ||
17 | #include "pmu_common.h" | 17 | #include "pmu_common.h" |
18 | #include "pmuif/gpmuif_pg_rppg.h" | ||
18 | 19 | ||
19 | /* PMU Command/Message Interfaces for Adaptive Power */ | 20 | /* PMU Command/Message Interfaces for Adaptive Power */ |
20 | /* Macro to get Histogram index */ | 21 | /* Macro to get Histogram index */ |
@@ -447,6 +448,7 @@ struct pmu_pg_msg { | |||
447 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; | 448 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; |
448 | /* TBD: other pg messages */ | 449 | /* TBD: other pg messages */ |
449 | union pmu_ap_msg ap_msg; | 450 | union pmu_ap_msg ap_msg; |
451 | struct nv_pmu_rppg_msg rppg_msg; | ||
450 | }; | 452 | }; |
451 | }; | 453 | }; |
452 | 454 | ||
@@ -478,7 +480,8 @@ enum { | |||
478 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | 480 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, |
479 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | 481 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, |
480 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | 482 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, |
481 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE | 483 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, |
484 | PMU_PMU_PG_CMD_ID_RPPG = 0x24, | ||
482 | }; | 485 | }; |
483 | 486 | ||
484 | struct pmu_pg_cmd_elpg_cmd { | 487 | struct pmu_pg_cmd_elpg_cmd { |
@@ -526,6 +529,7 @@ enum { | |||
526 | 529 | ||
527 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | 530 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) |
528 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | 531 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) |
532 | #define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) | ||
529 | 533 | ||
530 | struct pmu_pg_cmd_gr_init_param { | 534 | struct pmu_pg_cmd_gr_init_param { |
531 | u8 cmd_type; | 535 | u8 cmd_type; |
@@ -551,6 +555,7 @@ struct pmu_pg_cmd { | |||
551 | struct pmu_pg_cmd_gr_init_param gr_init_param; | 555 | struct pmu_pg_cmd_gr_init_param gr_init_param; |
552 | /* TBD: other pg commands */ | 556 | /* TBD: other pg commands */ |
553 | union pmu_ap_cmd ap_cmd; | 557 | union pmu_ap_cmd ap_cmd; |
558 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
554 | }; | 559 | }; |
555 | }; | 560 | }; |
556 | 561 | ||