diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-05 18:03:20 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-07 12:39:28 -0400 |
commit | 6675c03603669c667c6ffec34567eaf101a2d09d (patch) | |
tree | 99397eab8b2f031fbf8aa49b15046ebe9bffabb1 /drivers/gpu/nvgpu/gk20a | |
parent | 16658fd39da9021aeec08fe11c56d7877f723da7 (diff) |
gpu: nvgpu: Sync with register generator
Use re-generated register definitions. This synchronizes
kernel with the register generator.
Change-Id: I85a00f8f5c7bdfbc56cf4df909e5ae892d86f062
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120812
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index b9d083e3..a3ae664f 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -918,6 +918,10 @@ static inline u32 gr_fecs_host_int_status_r(void) | |||
918 | { | 918 | { |
919 | return 0x00409c18; | 919 | return 0x00409c18; |
920 | } | 920 | } |
921 | static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) | ||
922 | { | ||
923 | return (v & 0x1) << 16; | ||
924 | } | ||
921 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | 925 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) |
922 | { | 926 | { |
923 | return (v & 0x1) << 17; | 927 | return (v & 0x1) << 17; |
@@ -3114,6 +3118,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | |||
3114 | { | 3118 | { |
3115 | return 0x0; | 3119 | return 0x0; |
3116 | } | 3120 | } |
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) | ||
3122 | { | ||
3123 | return 0x00000000; | ||
3124 | } | ||
3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) | ||
3126 | { | ||
3127 | return 0x00000000; | ||
3128 | } | ||
3117 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | 3129 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) |
3118 | { | 3130 | { |
3119 | return 0x00504614; | 3131 | return 0x00504614; |
@@ -3130,14 +3142,6 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | |||
3130 | { | 3142 | { |
3131 | return 0x00419e24; | 3143 | return 0x00419e24; |
3132 | } | 3144 | } |
3133 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | ||
3134 | { | ||
3135 | return 0x00000000; | ||
3136 | } | ||
3137 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | ||
3138 | { | ||
3139 | return 0x00000000; | ||
3140 | } | ||
3141 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3145 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3142 | { | 3146 | { |
3143 | return 0x0050460c; | 3147 | return 0x0050460c; |