diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2017-04-19 14:07:05 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-12 13:14:37 -0400 |
commit | 5a4926f2918b84fccefb8ddf6dbaa7b6449735bf (patch) | |
tree | 792361e78f0e178281db15e675e00d87a6ee0e60 /drivers/gpu/nvgpu/gk20a | |
parent | d0955cad82c92699965f76c95c87150fbed70d3a (diff) |
gpu: nvgpu: pmu: add check before enabling elpg.
Do not enable/disable elpg if platform->can_elpg is false.
Bug 1870556
Change-Id: I82d1fc4efdccc518827a6150fd3c17f6112e2f4a
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1465816
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 5 |
3 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index cb54a1ca..edd98896 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1206,6 +1206,7 @@ static inline void get_exception_mmu_fault_info( | |||
1206 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | 1206 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) |
1207 | { | 1207 | { |
1208 | struct fifo_gk20a *f = NULL; | 1208 | struct fifo_gk20a *f = NULL; |
1209 | struct gk20a_platform *platform; | ||
1209 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1210 | u32 engine_enum = ENGINE_INVAL_GK20A; |
1210 | u32 inst_id = 0; | 1211 | u32 inst_id = 0; |
1211 | struct fifo_engine_info_gk20a *engine_info; | 1212 | struct fifo_engine_info_gk20a *engine_info; |
@@ -1216,6 +1217,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1216 | return; | 1217 | return; |
1217 | 1218 | ||
1218 | f = &g->fifo; | 1219 | f = &g->fifo; |
1220 | platform = dev_get_drvdata(g->dev); | ||
1219 | 1221 | ||
1220 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); | 1222 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); |
1221 | 1223 | ||
@@ -1228,7 +1230,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1228 | nvgpu_err(g, "unsupported engine_id %d", engine_id); | 1230 | nvgpu_err(g, "unsupported engine_id %d", engine_id); |
1229 | 1231 | ||
1230 | if (engine_enum == ENGINE_GR_GK20A) { | 1232 | if (engine_enum == ENGINE_GR_GK20A) { |
1231 | if (g->support_pmu && g->elpg_enabled) | 1233 | if (g->support_pmu && platform->can_elpg) |
1232 | gk20a_pmu_disable_elpg(g); | 1234 | gk20a_pmu_disable_elpg(g); |
1233 | /* resetting engine will alter read/write index. | 1235 | /* resetting engine will alter read/write index. |
1234 | * need to flush circular buffer before re-enabling FECS. | 1236 | * need to flush circular buffer before re-enabling FECS. |
@@ -1241,7 +1243,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1241 | /* resetting engine using mc_enable_r() is not | 1243 | /* resetting engine using mc_enable_r() is not |
1242 | enough, we do full init sequence */ | 1244 | enough, we do full init sequence */ |
1243 | gk20a_gr_reset(g); | 1245 | gk20a_gr_reset(g); |
1244 | if (g->support_pmu && g->elpg_enabled) | 1246 | if (g->support_pmu && platform->can_elpg) |
1245 | gk20a_pmu_enable_elpg(g); | 1247 | gk20a_pmu_enable_elpg(g); |
1246 | } | 1248 | } |
1247 | if ((engine_enum == ENGINE_GRCE_GK20A) || | 1249 | if ((engine_enum == ENGINE_GRCE_GK20A) || |
@@ -1466,6 +1468,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1466 | bool id_is_tsg) | 1468 | bool id_is_tsg) |
1467 | { | 1469 | { |
1468 | bool fake_fault; | 1470 | bool fake_fault; |
1471 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1469 | unsigned long fault_id; | 1472 | unsigned long fault_id; |
1470 | unsigned long engine_mmu_fault_id; | 1473 | unsigned long engine_mmu_fault_id; |
1471 | bool verbose = true; | 1474 | bool verbose = true; |
@@ -1476,7 +1479,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1476 | g->fifo.deferred_reset_pending = false; | 1479 | g->fifo.deferred_reset_pending = false; |
1477 | 1480 | ||
1478 | /* Disable power management */ | 1481 | /* Disable power management */ |
1479 | if (g->support_pmu && g->elpg_enabled) | 1482 | if (g->support_pmu && platform->can_elpg) |
1480 | gk20a_pmu_disable_elpg(g); | 1483 | gk20a_pmu_disable_elpg(g); |
1481 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) | 1484 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) |
1482 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, | 1485 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, |
@@ -1675,8 +1678,9 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1675 | gr_gpfifo_ctl_semaphore_access_enabled_f()); | 1678 | gr_gpfifo_ctl_semaphore_access_enabled_f()); |
1676 | 1679 | ||
1677 | /* It is safe to enable ELPG again. */ | 1680 | /* It is safe to enable ELPG again. */ |
1678 | if (g->support_pmu && g->elpg_enabled) | 1681 | if (g->support_pmu && platform->can_elpg) |
1679 | gk20a_pmu_enable_elpg(g); | 1682 | gk20a_pmu_enable_elpg(g); |
1683 | |||
1680 | return verbose; | 1684 | return verbose; |
1681 | } | 1685 | } |
1682 | 1686 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 2d87911d..bd5f44a4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3126,6 +3126,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3126 | struct nvgpu_alloc_obj_ctx_args *args) | 3126 | struct nvgpu_alloc_obj_ctx_args *args) |
3127 | { | 3127 | { |
3128 | struct gk20a *g = c->g; | 3128 | struct gk20a *g = c->g; |
3129 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
3129 | struct fifo_gk20a *f = &g->fifo; | 3130 | struct fifo_gk20a *f = &g->fifo; |
3130 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 3131 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
3131 | struct tsg_gk20a *tsg = NULL; | 3132 | struct tsg_gk20a *tsg = NULL; |
@@ -3280,7 +3281,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3280 | 3281 | ||
3281 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; | 3282 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; |
3282 | 3283 | ||
3283 | if (g->support_pmu) | 3284 | if (g->support_pmu && platform->can_elpg) |
3284 | gk20a_pmu_enable_elpg(g); | 3285 | gk20a_pmu_enable_elpg(g); |
3285 | } | 3286 | } |
3286 | 3287 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 26ce66f1..af22b13f 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -4936,6 +4936,7 @@ clean_up: | |||
4936 | int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | 4936 | int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) |
4937 | { | 4937 | { |
4938 | u32 status = 0; | 4938 | u32 status = 0; |
4939 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
4939 | 4940 | ||
4940 | if (enable_pg == true) { | 4941 | if (enable_pg == true) { |
4941 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 4942 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -4945,7 +4946,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4945 | if (g->ops.pmu.pmu_lpwr_enable_pg) | 4946 | if (g->ops.pmu.pmu_lpwr_enable_pg) |
4946 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, | 4947 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, |
4947 | true); | 4948 | true); |
4948 | } else if (g->support_pmu) | 4949 | } else if (g->support_pmu && platform->can_elpg) |
4949 | status = gk20a_pmu_enable_elpg(g); | 4950 | status = gk20a_pmu_enable_elpg(g); |
4950 | } else if (enable_pg == false) { | 4951 | } else if (enable_pg == false) { |
4951 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 4952 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -4955,7 +4956,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4955 | if (g->ops.pmu.pmu_lpwr_disable_pg) | 4956 | if (g->ops.pmu.pmu_lpwr_disable_pg) |
4956 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, | 4957 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, |
4957 | true); | 4958 | true); |
4958 | } else if (g->support_pmu) | 4959 | } else if (g->support_pmu && platform->can_elpg) |
4959 | status = gk20a_pmu_disable_elpg(g); | 4960 | status = gk20a_pmu_disable_elpg(g); |
4960 | } | 4961 | } |
4961 | 4962 | ||