gpu: nvgpu: Implement get_rate/set_rate as GPU op

Move clock APIs from gk20a_platform to gpu_ops. At the same time
allow use of internal get_rate/set_rate for querying both GPCCLK
and PWRCLK on iGPU.

At the same time we can replace calls to clk framework with the
new HAL and drop direct dependency to clk framework.

gp10b ops were replaced as a whole at HAL initialization. That
replaces anything set in platform probe stage, so reduce that to
touch only clock gating regs.

Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300113
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 10 insertions, 15 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5a4eaf39..695d2d1a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -691,6 +691,8 @@ struct gpu_ops {
                 int (*suspend_clk_support)(struct gk20a *g);
                 u32 (*get_crystal_clk_hz)(struct gk20a *g);
                 unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain);
+                unsigned long (*get_rate)(struct gk20a *g, u32 api_domain);
+                int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate);
         } clk;
         struct {
                 u32 (*get_arbiter_clk_domains)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
index edf92de6..b9e92f15 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.c
@@ -19,10 +19,8 @@
 #include <linux/devfreq.h>
 #include <linux/debugfs.h>
 #include <linux/types.h>
-#include <linux/clk.h>
 #include <linux/export.h>
 #include <linux/slab.h>
-#include <linux/clk/tegra.h>
 #include <soc/tegra/chip-id.h>
 #include <linux/platform_data/tegra_edp.h>
 #include <linux/pm_qos.h>
@@ -188,11 +186,11 @@ static int gk20a_scale_target(struct device *dev, unsigned long *freq,
         if (rounded_rate == g->last_freq)
                 return 0;
 
-        if (platform->clk_get_rate(dev) == rounded_rate)
+        if (g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK) == rounded_rate)
                 *freq = rounded_rate;
         else {
-                platform->clk_set_rate(dev, rounded_rate);
-                *freq = platform->clk_get_rate(dev);
+                g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, rounded_rate);
+                *freq = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK);
         }
 
         g->last_freq = *freq;
@@ -321,7 +319,7 @@ static int gk20a_scale_get_dev_status(struct device *dev,
 
         /* Make sure there are correct values for the current frequency */
         profile->dev_stat.current_frequency =
-                                platform->clk_get_rate(profile->dev);
+                                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK);
 
         /* Update load estimate */
         update_load_estimate_gpmu(dev);
@@ -344,8 +342,8 @@ static int gk20a_scale_get_dev_status(struct device *dev,
 
 static int get_cur_freq(struct device *dev, unsigned long *freq)
 {
-        struct gk20a_platform *platform = dev_get_drvdata(dev);
-        *freq = platform->clk_get_rate(dev);
+        struct gk20a *g = get_gk20a(dev);
+        *freq = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK);
         return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
index 9eb8e835..23725b8b 100644
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
@@ -143,7 +143,7 @@ int gk20a_init_hal(struct gk20a *g)
         struct gpu_ops *gops = &g->ops;
         struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
 
-        *gops = gk20a_ops;
+        gops->clock_gating = gk20a_ops.clock_gating;
         gops->privsecurity = 0;
         gops->securegpccs = 0;
         gops->pmupstate = false;
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
index 42be2271..b23d0091 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
@@ -196,11 +196,8 @@ struct gk20a_platform {
                                 unsigned long **freqs, int *num_freqs);
 
         /* clk related supported functions */
-        unsigned long (*clk_get_rate)(struct device *dev);
         long (*clk_round_rate)(struct device *dev,
                                 unsigned long rate);
-        int (*clk_set_rate)(struct device *dev,
-                                unsigned long rate);
 
         /* Called to register GPCPLL with common clk framework */
         int (*clk_register)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 7e37762c..c7e68f44 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -18,7 +18,6 @@
 
 #include <linux/delay.h>        /* for mdelay */
 #include <linux/firmware.h>
-#include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/debugfs.h>
 #include <linux/dma-mapping.h>
@@ -2474,7 +2473,6 @@ int pmu_reset(struct pmu_gk20a *pmu)
 int pmu_bootstrap(struct pmu_gk20a *pmu)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
-        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
         struct mm_gk20a *mm = &g->mm;
         struct pmu_ucode_desc *desc = pmu->desc;
         u64 addr_code, addr_data, addr_load;
@@ -2499,7 +2497,7 @@ int pmu_bootstrap(struct pmu_gk20a *pmu)
                 pmu, GK20A_PMU_DMAIDX_VIRT);
 
         g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                clk_get_rate(platform->clk[1]));
+                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
 
         addr_args = (pwr_falcon_hwcfg_dmem_size_v(
                 gk20a_readl(g, pwr_falcon_hwcfg_r()))