gpu: nvgpu: Do not disable GRFIFO access when resetting GR

gk20a_init_gr_prepare() is called only when initializing GR from reset.
In those cases there is no need to disable GRFIFO access. Remove the
corresponding code. It also gets rid of one extra dependency to MC
registers.

JIRA NVGPU-954

Change-Id: I935e65f236e0f29ab224787d20e017d8c67e69e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822309
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 4a460d02..6c885b59 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4705,17 +4705,8 @@ static void gr_gk20a_load_gating_prod(struct gk20a *g)
 
 static int gk20a_init_gr_prepare(struct gk20a *g)
 {
-        u32 gpfifo_ctrl, pmc_en;
         u32 err = 0;
 
-        /* disable fifo access */
-        pmc_en = gk20a_readl(g, mc_enable_r());
-        if (pmc_en & mc_enable_pgraph_enabled_f()) {
-                gpfifo_ctrl = gk20a_readl(g, gr_gpfifo_ctl_r());
-                gpfifo_ctrl &= ~gr_gpfifo_ctl_access_enabled_f();
-                gk20a_writel(g, gr_gpfifo_ctl_r(), gpfifo_ctrl);
-        }
-
         /* reset gr engine */
         g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() |
                         mc_enable_blg_enabled_f() |