gpu: nvgpu: remove dependency on linux header for regops_gk20a*

This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.

1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.

JIRA NVGPU-417

Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 63 insertions, 20 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 11a99bff..33d40cd5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -949,7 +949,7 @@ struct gpu_ops {
         } debug;
         struct {
                 int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
-                            struct nvgpu_dbg_gpu_reg_op *ops,
+                            struct nvgpu_dbg_reg_op *ops,
                             u64 num_ops);
                 int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
                                         bool disable_powergate);
@@ -1206,7 +1206,7 @@ struct gk20a {
         int dbg_timeout_disabled_refcount; /*refcount for timeout disable */
 
         /* must have dbg_sessions_lock before use */
-        struct nvgpu_dbg_gpu_reg_op *dbg_regops_tmp_buf;
+        struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf;
         u32 dbg_regops_tmp_buf_ops;
 
         /* For perfbuf mapping */
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 03e1d567..82695e44 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -7749,7 +7749,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
 }
 
 int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
-                            struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
+                            struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
                             u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
                             bool ch_is_curr_ctx)
 {
@@ -7990,7 +7990,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 }
 
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
-                          struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
+                          struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
                           u32 num_ctx_wr_ops, u32 num_ctx_rd_ops)
 {
         struct gk20a *g = ch->g;
@@ -8279,7 +8279,7 @@ void gk20a_gr_resume_all_sms(struct gk20a *g)
 int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable)
 {
-        struct nvgpu_dbg_gpu_reg_op *ops;
+        struct nvgpu_dbg_reg_op *ops;
         unsigned int i = 0, sm_id;
         int err;
         u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -8453,7 +8453,7 @@ int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch)
 {
         int err = 0;
         u32     cache_ctrl, regval;
-        struct nvgpu_dbg_gpu_reg_op ops;
+        struct nvgpu_dbg_reg_op ops;
 
         ops.op     = REGOP(READ_32);
         ops.type   = REGOP(TYPE_GR_CTX);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 0df88988..5a5809fc 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -604,12 +604,12 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
 
 int gk20a_gr_suspend(struct gk20a *g);
 
-struct nvgpu_dbg_gpu_reg_op;
+struct nvgpu_dbg_reg_op;
 int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
-                          struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
+                          struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
                           u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
 int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
-                            struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
+                            struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
                             u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
                             bool ch_is_curr_ctx);
 int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index f0cf5205..06cd5051 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -22,9 +22,6 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <linux/err.h>
-#include <uapi/linux/nvgpu.h>
-
 #include "gk20a.h"
 #include "gr_gk20a.h"
 #include "dbg_gpu_gk20a.h"
@@ -377,12 +374,12 @@ static const u32 gk20a_qctl_whitelist_ranges_count =
 
 static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
                              u32 *ctx_rd_count, u32 *ctx_wr_count,
-                             struct nvgpu_dbg_gpu_reg_op *ops,
+                             struct nvgpu_dbg_reg_op *ops,
                              u32 op_count);
 
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
-                      struct nvgpu_dbg_gpu_reg_op *ops,
+                      struct nvgpu_dbg_reg_op *ops,
                       u64 num_ops)
 {
         int err = 0;
@@ -519,7 +516,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 
 
 static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s,
-                                struct nvgpu_dbg_gpu_reg_op *op)
+                                struct nvgpu_dbg_reg_op *op)
 {
         int err = 0;
 
@@ -559,7 +556,7 @@ static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s,
 }
 
 static bool check_whitelists(struct dbg_session_gk20a *dbg_s,
-                          struct nvgpu_dbg_gpu_reg_op *op, u32 offset)
+                          struct nvgpu_dbg_reg_op *op, u32 offset)
 {
         struct gk20a *g = dbg_s->g;
         bool valid = false;
@@ -630,7 +627,7 @@ static bool check_whitelists(struct dbg_session_gk20a *dbg_s,
 
 /* note: the op here has already been through validate_reg_op_info */
 static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s,
-                                  struct nvgpu_dbg_gpu_reg_op *op)
+                                  struct nvgpu_dbg_reg_op *op)
 {
         int err;
         u32 buf_offset_lo, buf_offset_addr, num_offsets, offset;
@@ -689,7 +686,7 @@ static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s,
 
 static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
                             u32 *ctx_rd_count, u32 *ctx_wr_count,
-                            struct nvgpu_dbg_gpu_reg_op *ops,
+                            struct nvgpu_dbg_reg_op *ops,
                             u32 op_count)
 {
         u32 i;
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
index 4db79397..236fb52c 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
@@ -24,17 +24,63 @@
 #ifndef REGOPS_GK20A_H
 #define REGOPS_GK20A_H
 
+/*
+ * Register operations
+ * All operations are targeted towards first channel
+ * attached to debug session
+ */
+/* valid op values */
+#define NVGPU_DBG_REG_OP_READ_32                             (0x00000000)
+#define NVGPU_DBG_REG_OP_WRITE_32                            (0x00000001)
+#define NVGPU_DBG_REG_OP_READ_64                             (0x00000002)
+#define NVGPU_DBG_REG_OP_WRITE_64                            (0x00000003)
+/* note: 8b ops are unsupported */
+#define NVGPU_DBG_REG_OP_READ_08                             (0x00000004)
+#define NVGPU_DBG_REG_OP_WRITE_08                            (0x00000005)
+
+/* valid type values */
+#define NVGPU_DBG_REG_OP_TYPE_GLOBAL                         (0x00000000)
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX                         (0x00000001)
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC                     (0x00000002)
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM                      (0x00000004)
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP                    (0x00000008)
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP                    (0x00000010)
+/*#define NVGPU_DBG_REG_OP_TYPE_FB                           (0x00000020)*/
+#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD                    (0x00000040)
+
+/* valid status values */
+#define NVGPU_DBG_REG_OP_STATUS_SUCCESS                      (0x00000000)
+#define NVGPU_DBG_REG_OP_STATUS_INVALID_OP                   (0x00000001)
+#define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE                 (0x00000002)
+#define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET               (0x00000004)
+#define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP               (0x00000008)
+#define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK                 (0x00000010)
+
+struct nvgpu_dbg_reg_op {
+        __u8    op;
+        __u8    type;
+        __u8    status;
+        __u8    quad;
+        __u32   group_mask;
+        __u32   sub_group_mask;
+        __u32   offset;
+        __u32   value_lo;
+        __u32   value_hi;
+        __u32   and_n_mask_lo;
+        __u32   and_n_mask_hi;
+};
+
 struct regop_offset_range {
         u32 base:24;
         u32 count:8;
 };
 
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
-                      struct nvgpu_dbg_gpu_reg_op *ops,
+                      struct nvgpu_dbg_reg_op *ops,
                       u64 num_ops);
 
 /* turn seriously unwieldy names -> something shorter */
-#define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x
+#define REGOP(x) NVGPU_DBG_REG_OP_##x
 
 bool reg_op_is_gr_ctx(u8 type);
 bool reg_op_is_read(u8 op);