diff options
author | Lakshmanan M <lm@nvidia.com> | 2016-05-11 07:17:08 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-13 13:01:56 -0400 |
commit | 50c6c9cfcd040742f3d242993576c65842006f92 (patch) | |
tree | fa61f863f2bc7b0039005c37bcaa5596b22ffd0d /drivers/gpu/nvgpu/gk20a | |
parent | 67535de642c485eae0f9529ae8148c9ea071b9c1 (diff) |
gpu: nvgpu: Add support for multiple PBDMAs
Added support for multiple PBDMAs handling during
fifo_pbdma_isr and gk20a_init_fifo_reset_enable_hw
use case.
JIRA DNVGPU-26
Change-Id: I5f013c5373f7a4b80a8de8863f0e175576ed4c22
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1145591
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 71400331..cdbb4a6c 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -397,7 +397,8 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
397 | fifo_fb_timeout_period_max_f()); | 397 | fifo_fb_timeout_period_max_f()); |
398 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); | 398 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); |
399 | 399 | ||
400 | for (i = 0; i < pbdma_timeout__size_1_v(); i++) { | 400 | /* write pbdma timeout value */ |
401 | for (i = 0; i < host_num_pbdma; i++) { | ||
401 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); | 402 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); |
402 | timeout = set_field(timeout, pbdma_timeout_period_m(), | 403 | timeout = set_field(timeout, pbdma_timeout_period_m(), |
403 | pbdma_timeout_period_max_f()); | 404 | pbdma_timeout_period_max_f()); |
@@ -1741,10 +1742,11 @@ static u32 fifo_pbdma_isr(struct gk20a *g, u32 fifo_intr) | |||
1741 | struct device *dev = dev_from_gk20a(g); | 1742 | struct device *dev = dev_from_gk20a(g); |
1742 | struct fifo_gk20a *f = &g->fifo; | 1743 | struct fifo_gk20a *f = &g->fifo; |
1743 | u32 clear_intr = 0, i; | 1744 | u32 clear_intr = 0, i; |
1745 | u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); | ||
1744 | u32 pbdma_pending = gk20a_readl(g, fifo_intr_pbdma_id_r()); | 1746 | u32 pbdma_pending = gk20a_readl(g, fifo_intr_pbdma_id_r()); |
1745 | 1747 | ||
1746 | for (i = 0; i < fifo_intr_pbdma_id_status__size_1_v(); i++) { | 1748 | for (i = 0; i < host_num_pbdma; i++) { |
1747 | if (fifo_intr_pbdma_id_status_f(pbdma_pending, i)) { | 1749 | if (fifo_intr_pbdma_id_status_v(pbdma_pending, i)) { |
1748 | gk20a_dbg(gpu_dbg_intr, "pbdma id %d intr pending", i); | 1750 | gk20a_dbg(gpu_dbg_intr, "pbdma id %d intr pending", i); |
1749 | clear_intr |= | 1751 | clear_intr |= |
1750 | gk20a_fifo_handle_pbdma_intr(dev, g, f, i); | 1752 | gk20a_fifo_handle_pbdma_intr(dev, g, f, i); |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h index 07e2b4f8..c5c95cdf 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h | |||
@@ -362,6 +362,10 @@ static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) | |||
362 | { | 362 | { |
363 | return (v & 0x1) << (0 + i*1); | 363 | return (v & 0x1) << (0 + i*1); |
364 | } | 364 | } |
365 | static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | ||
366 | { | ||
367 | return (r >> (0 + i*1)) & 0x1; | ||
368 | } | ||
365 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | 369 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) |
366 | { | 370 | { |
367 | return 0x00000001; | 371 | return 0x00000001; |