gpu: nvgpu: Rearrange the static inline code

In order to avoid the circular dependencies,
rearrange the static inline functions from
gk20a.h file.

Moved gk20a_gr_flush_channel_tlb function to
gr_gk20a.c and removed the #include gr_gk20a.h
from gk20a.h

Added a helper function utils.h to
move all generic static inline functions which
have no reference to gpu related structures.

ptimer related functions are moved to
ptimer.h

Implementations for as and pmu are moved to
corresponding files.

JIRA NVGPU-624

Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1781941
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 16 insertions, 61 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 53134f71..8d6c3b70 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -42,6 +42,7 @@
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/os_sched.h>
 #include <nvgpu/log2.h>
+#include <nvgpu/ptimer.h>
 
 #include "gk20a.h"
 #include "dbg_gpu_gk20a.h"
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 57cb0019..9086e468 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -40,6 +40,7 @@
 #include <nvgpu/barrier.h>
 #include <nvgpu/ctxsw_trace.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/ptimer.h>
 
 #include "gk20a.h"
 #include "mm_gk20a.h"
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index afd18658..4fe93e3b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -64,12 +64,12 @@ struct nvgpu_ctxsw_trace_filter;
 #include <nvgpu/nvlink.h>
 #include <nvgpu/sim.h>
 #include <nvgpu/ecc.h>
+#include <nvgpu/utils.h>
 
 #include "clk_gk20a.h"
 #include "ce2_gk20a.h"
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
-#include "gr_gk20a.h"
 #include "pmu_gk20a.h"
 #include "priv_ring_gk20a.h"
 #include "therm_gk20a.h"
@@ -78,10 +78,6 @@ struct nvgpu_ctxsw_trace_filter;
 #include "pmgr/pmgr.h"
 #include "therm/thrm.h"
 
-/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
-    32 ns is the resolution of ptimer. */
-#define PTIMER_REF_FREQ_HZ                      31250000
-
 #ifdef CONFIG_DEBUG_FS
 struct railgate_stats {
         unsigned long last_rail_gate_start;
@@ -1652,50 +1648,8 @@ enum gk20a_nonstall_ops {
 void __nvgpu_check_gpu_state(struct gk20a *g);
 void __gk20a_warn_on_no_regs(void);
 
-/* convenience */
-static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
-{
-        return container_of(as, struct gk20a, as);
-}
-static inline struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu)
-{
-        return container_of(pmu, struct gk20a, pmu);
-}
-
-static inline u32 u64_hi32(u64 n)
-{
-        return (u32)((n >> 32) & ~(u32)0);
-}
-
-static inline u32 u64_lo32(u64 n)
-{
-        return (u32)(n & ~(u32)0);
-}
-
-static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo)
-{
-        return  (((u64)hi) << 32) | (u64)lo;
-}
-
-static inline u32 set_field(u32 val, u32 mask, u32 field)
-{
-        return ((val & ~mask) | field);
-}
-
-static inline u32 get_field(u32 reg, u32 mask)
-{
-        return (reg & mask);
-}
-
-/* invalidate channel lookup tlb */
-static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
-{
-        nvgpu_spinlock_acquire(&gr->ch_tlb_lock);
-        memset(gr->chid_tlb, 0,
-                sizeof(struct gr_channel_map_tlb_entry) *
-                GR_CHANNEL_MAP_TLB_SIZE);
-        nvgpu_spinlock_release(&gr->ch_tlb_lock);
-}
+struct gk20a *gk20a_from_as(struct gk20a_as *as);
+struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu);
 
 /* classes that the device supports */
 /* TBD: get these from an open-sourced SDK? */
@@ -1736,18 +1690,6 @@ int gk20a_wait_for_idle(struct gk20a *g);
 
 int gk20a_init_gpu_characteristics(struct gk20a *g);
 
-static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq)
-{
-        return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq);
-}
-static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
-{
-        if (((timeout*10) % scale10x) >= (scale10x/2))
-                return ((timeout * 10) / scale10x) + 1;
-        else
-                return (timeout * 10) / scale10x;
-}
-
 int gk20a_prepare_poweroff(struct gk20a *g);
 int gk20a_finalize_poweron(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 38570041..40bd5413 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8777,3 +8777,13 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g)
 
         return global_esr_mask;
 }
+
+/* invalidate channel lookup tlb */
+void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
+{
+        nvgpu_spinlock_acquire(&gr->ch_tlb_lock);
+        memset(gr->chid_tlb, 0,
+                sizeof(struct gr_channel_map_tlb_entry) *
+                GR_CHANNEL_MAP_TLB_SIZE);
+        nvgpu_spinlock_release(&gr->ch_tlb_lock);
+}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 92e1dff5..0c6be57b 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -857,4 +857,5 @@ void gk20a_gr_destroy_ctx_buffer(struct gk20a *g,
         struct gr_ctx_buffer_desc *desc);
 int gk20a_gr_alloc_ctx_buffer(struct gk20a *g,
         struct gr_ctx_buffer_desc *desc, size_t size);
+void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr);
 #endif /*__GR_GK20A_H__*/