diff options
author | Vaibhav Kachore <vkachore@nvidia.com> | 2018-07-03 07:51:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-10 21:14:16 -0400 |
commit | 503d489dba278136ea0e4241d000018682989da5 (patch) | |
tree | 29b95d43aaf47b50f2abda9a4e16153afe070c25 /drivers/gpu/nvgpu/gk20a | |
parent | e14fdcd8f1f4125da697433b1744b1e4e4f15b09 (diff) |
gpu: nvgpu: Initialize hwpm perfmons (engine_sel)
- For Mode-E ctxsw it is required that engine_sel
is set to 0xFFFFFFFF.
- Default 0 is a valid signal and causes problems.
Bug 2106999
Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770755
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ce0a6563..b677419c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -312,6 +312,7 @@ struct gpu_ops { | |||
312 | struct channel_gk20a *c, | 312 | struct channel_gk20a *c, |
313 | u64 gpu_va, | 313 | u64 gpu_va, |
314 | u32 mode); | 314 | u32 mode); |
315 | void (*init_hwpm_pmm_register)(struct gk20a *g); | ||
315 | int (*dump_gr_regs)(struct gk20a *g, | 316 | int (*dump_gr_regs)(struct gk20a *g, |
316 | struct gk20a_debug_output *o); | 317 | struct gk20a_debug_output *o); |
317 | int (*update_pc_sampling)(struct channel_gk20a *ch, | 318 | int (*update_pc_sampling)(struct channel_gk20a *ch, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 3f49fbf7..c70c1cd4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1782,6 +1782,11 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1782 | return -ENOMEM; | 1782 | return -ENOMEM; |
1783 | } | 1783 | } |
1784 | } | 1784 | } |
1785 | |||
1786 | if (mode == NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW && | ||
1787 | g->ops.gr.init_hwpm_pmm_register) { | ||
1788 | g->ops.gr.init_hwpm_pmm_register(g); | ||
1789 | } | ||
1785 | } | 1790 | } |
1786 | 1791 | ||
1787 | data = nvgpu_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); | 1792 | data = nvgpu_mem_rd(g, gr_mem, ctxsw_prog_main_image_pm_o()); |