gpu: nvgpu: Sync gk20a and gm20b headers

Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.

Bug 1567274

Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit

12 files changed, 279 insertions, 297 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 58dde415..9f2e0017 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -186,9 +186,9 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
         }
 
         /* set new timeslice */
-        gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(),
+        gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(),
                 value | (shift << 12) |
-                fifo_eng_timeslice_enable_true_f());
+                fifo_runlist_timeslice_enable_true_f());
 
         /* enable channel */
         gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
@@ -249,10 +249,10 @@ int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
                 pbdma_acquire_timeout_man_max_f() |
                 pbdma_acquire_timeout_en_disable_f());
 
-        gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(),
-                fifo_eng_timeslice_timeout_128_f() |
-                fifo_eng_timeslice_timescale_3_f() |
-                fifo_eng_timeslice_enable_true_f());
+        gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(),
+                fifo_runlist_timeslice_timeout_128_f() |
+                fifo_runlist_timeslice_timescale_3_f() |
+                fifo_runlist_timeslice_enable_true_f());
 
         gk20a_mem_wr32(inst_ptr, ram_fc_pb_timeslice_w(),
                 fifo_pb_timeslice_timeout_16_f() |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h
deleted file mode 100644
index 66bf01b0..00000000
--- a/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-/*
- * Function naming determines intended use:
- *
- *     <x>_r(void) : Returns the offset for register <x>.
- *
- *     <x>_o(void) : Returns the offset for element <x>.
- *
- *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
- *
- *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
- *
- *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
- *         and masked to place it at field <y> of register <x>.  This value
- *         can be |'d with others to produce a full register value for
- *         register <x>.
- *
- *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
- *         value can be ~'d and then &'d to clear the value of field <y> for
- *         register <x>.
- *
- *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
- *         to place it at field <y> of register <x>.  This value can be |'d
- *         with others to produce a full register value for <x>.
- *
- *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
- *         <x> value 'r' after being shifted to place its LSB at bit 0.
- *         This value is suitable for direct comparison with other unshifted
- *         values appropriate for use in field <y> of register <x>.
- *
- *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
- *         field <y> of register <x>.  This value is suitable for direct
- *         comparison with unshifted values appropriate for use in field <y>
- *         of register <x>.
- */
-#ifndef _hw_chiplet_pwr_gk20a_h_
-#define _hw_chiplet_pwr_gk20a_h_
-
-static inline u32 chiplet_pwr_gpcs_weight_6_r(void)
-{
-        return 0x0010e018;
-}
-static inline u32 chiplet_pwr_gpcs_weight_7_r(void)
-{
-        return 0x0010e01c;
-}
-static inline u32 chiplet_pwr_gpcs_config_1_r(void)
-{
-        return 0x0010e03c;
-}
-static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void)
-{
-        return 0x1;
-}
-static inline u32 chiplet_pwr_fbps_weight_0_r(void)
-{
-        return 0x0010e100;
-}
-static inline u32 chiplet_pwr_fbps_weight_1_r(void)
-{
-        return 0x0010e104;
-}
-static inline u32 chiplet_pwr_fbps_config_1_r(void)
-{
-        return 0x0010e13c;
-}
-static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void)
-{
-        return 0x1;
-}
-#endif
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h
index 1c50d0d5..6b8b6718 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h
@@ -62,6 +62,10 @@ static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
 {
         return 0x0;
 }
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1;
+}
 static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
 {
         return (r >> 15) & 0x1;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
index f549bac4..757ae3f0 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
@@ -114,19 +114,19 @@ static inline u32 fifo_eng_runlist_pending_true_f(void)
 {
         return 0x100000;
 }
-static inline u32 fifo_eng_timeslice_r(u32 i)
+static inline u32 fifo_runlist_timeslice_r(u32 i)
 {
         return 0x00002310 + i*4;
 }
-static inline u32 fifo_eng_timeslice_timeout_128_f(void)
+static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
 {
         return 0x80;
 }
-static inline u32 fifo_eng_timeslice_timescale_3_f(void)
+static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
 {
         return 0x3000;
 }
-static inline u32 fifo_eng_timeslice_enable_true_f(void)
+static inline u32 fifo_runlist_timeslice_enable_true_f(void)
 {
         return 0x10000000;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
index e0118946..45ae59d6 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -142,6 +142,10 @@ static inline u32 gmmu_pte_valid_true_f(void)
 {
         return 0x1;
 }
+static inline u32 gmmu_pte_valid_false_f(void)
+{
+        return 0x0;
+}
 static inline u32 gmmu_pte_address_sys_f(u32 v)
 {
         return (v & 0xfffffff) << 4;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index f18e19be..463443d6 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -2618,30 +2618,6 @@ static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
 {
         return 0x10000000;
 }
-static inline u32 gr_gpcs_tpcs_l1c_pm_r(void)
-{
-        return 0x00419ca8;
-}
-static inline u32 gr_gpcs_tpcs_l1c_pm_enable_m(void)
-{
-        return 0x1 << 31;
-}
-static inline u32 gr_gpcs_tpcs_l1c_pm_enable_enable_f(void)
-{
-        return 0x80000000;
-}
-static inline u32 gr_gpcs_tpcs_l1c_cfg_r(void)
-{
-        return 0x00419cb8;
-}
-static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(void)
-{
-        return 0x1 << 31;
-}
-static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f(void)
-{
-        return 0x80000000;
-}
 static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
 {
         return 0x00419c00;
@@ -2654,26 +2630,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
 {
         return 0x8;
 }
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void)
-{
-        return 0x00419e00;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void)
-{
-        return 0x1 << 7;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void)
-{
-        return 0x80;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void)
-{
-        return 0x1 << 15;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void)
-{
-        return 0x8000;
-}
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
 {
         return 0x00419e44;
@@ -2906,14 +2862,6 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 {
         return 0x00419f70;
 }
-static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(void)
-{
-        return 0x1 << 1;
-}
-static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f(void)
-{
-        return 0x2;
-}
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
         return 0x1 << 4;
@@ -2938,18 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
         return (v & 0x1) << 0;
 }
-static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(void)
-{
-        return 0x1 << 16;
-}
-static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f(void)
-{
-        return 0x10000;
-}
-static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void)
-{
-        return 0x00419ed0;
-}
 static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
 {
         return 0x0041be08;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h
index f60b34e2..6db5654b 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h
@@ -54,6 +54,14 @@ static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
 {
         return 0x001410c8;
 }
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00141200;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017ea00;
+}
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
 {
         return 0x00141104;
@@ -104,7 +112,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
 }
 static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
 {
-        return 0x0017e8c8;
+        return 0x001410c8;
 }
 static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
 {
@@ -242,4 +250,188 @@ static inline u32 ltc_ltc0_ltss_intr_r(void)
 {
         return 0x00140820;
 }
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e820;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1 << 20;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x00141020;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e910;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e914;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x00140910;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x00140914;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h
index d7d26b80..35312bd4 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h
@@ -290,6 +290,42 @@ static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
 {
         return (v & 0x1) << 1;
 }
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180 + i*16;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184 + i*16;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188 + i*16;
+}
 static inline u32 pwr_falcon_bootvec_r(void)
 {
         return 0x0010a104;
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
index a039685e..0f4f6726 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
@@ -318,7 +318,7 @@ static inline u32 ram_fc_chid_id_w(void)
 {
         return 0;
 }
-static inline u32 ram_fc_eng_timeslice_w(void)
+static inline u32 ram_fc_runlist_timeslice_w(void)
 {
         return 62;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h
index 5d6397b4..42a31c5d 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -66,70 +66,10 @@ static inline u32 therm_evt_ext_therm_2_r(void)
 {
         return 0x00020708;
 }
-static inline u32 therm_evt_ba_w0_t1h_r(void)
-{
-        return 0x00020750;
-}
 static inline u32 therm_weight_1_r(void)
 {
         return 0x00020024;
 }
-static inline u32 therm_peakpower_config1_r(u32 i)
-{
-        return 0x00020154 + i*4;
-}
-static inline u32 therm_peakpower_config1_window_period_2m_v(void)
-{
-        return 0x0000000f;
-}
-static inline u32 therm_peakpower_config1_window_period_2m_f(void)
-{
-        return 0xf;
-}
-static inline u32 therm_peakpower_config1_ba_sum_shift_s(void)
-{
-        return 6;
-}
-static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v)
-{
-        return (v & 0x3f) << 8;
-}
-static inline u32 therm_peakpower_config1_ba_sum_shift_m(void)
-{
-        return 0x3f << 8;
-}
-static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r)
-{
-        return (r >> 8) & 0x3f;
-}
-static inline u32 therm_peakpower_config1_ba_sum_shift_20_f(void)
-{
-        return 0x1400;
-}
-static inline u32 therm_peakpower_config1_window_en_enabled_f(void)
-{
-        return 0x80000000;
-}
-static inline u32 therm_peakpower_config2_r(u32 i)
-{
-        return 0x00020170 + i*4;
-}
-static inline u32 therm_peakpower_config4_r(u32 i)
-{
-        return 0x000201c0 + i*4;
-}
-static inline u32 therm_peakpower_config6_r(u32 i)
-{
-        return 0x00020270 + i*4;
-}
-static inline u32 therm_peakpower_config8_r(u32 i)
-{
-        return 0x000202e8 + i*4;
-}
-static inline u32 therm_peakpower_config9_r(u32 i)
-{
-        return 0x000202f4 + i*4;
-}
 static inline u32 therm_config1_r(void)
 {
         return 0x00020050;
@@ -222,4 +162,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void)
 {
         return 0xffffffff << 0;
 }
+static inline u32 therm_clk_slowdown_r(u32 i)
+{
+        return 0x00020160 + i*4;
+}
+static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
+{
+        return (v & 0x3f) << 16;
+}
+static inline u32 therm_clk_slowdown_idle_factor_m(void)
+{
+        return 0x3f << 16;
+}
+static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
+{
+        return (r >> 16) & 0x3f;
+}
+static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
+{
+        return 0x0;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
index 826e9bd1..3b0aa05b 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,10 @@ static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
 {
         return (v & 0xff) << 0;
 }
+static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
+{
+        return 0xff << 0;
+}
 static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
 {
         return (r >> 0) & 0xff;
@@ -130,6 +134,10 @@ static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
 {
         return (v & 0x3f) << 16;
 }
+static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
+{
+        return 0x3f << 16;
+}
 static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
 {
         return (r >> 16) & 0x3f;
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
index da911979..b02113ad 100644
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
@@ -20,7 +20,6 @@
  */
 
 #include "gk20a.h"
-#include "hw_chiplet_pwr_gk20a.h"
 #include "hw_gr_gk20a.h"
 #include "hw_therm_gk20a.h"
 
@@ -45,78 +44,6 @@ static int gk20a_init_therm_setup_hw(struct gk20a *g)
         gk20a_writel(g, therm_evt_ext_therm_2_r(),
                 NV_THERM_EVT_EXT_THERM_2_INIT);
 
-/*
-        u32 data;
-
-        data = gk20a_readl(g, gr_gpcs_tpcs_l1c_cfg_r());
-        data = set_field(data, gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(),
-                gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f());
-        gk20a_writel(g, gr_gpcs_tpcs_l1c_cfg_r(), data);
-
-        data = gk20a_readl(g, gr_gpcs_tpcs_l1c_pm_r());
-        data = set_field(data, gr_gpcs_tpcs_l1c_pm_enable_m(),
-                gr_gpcs_tpcs_l1c_pm_enable_enable_f());
-        gk20a_writel(g, gr_gpcs_tpcs_l1c_pm_r(), data);
-
-        data = gk20a_readl(g, gr_gpcs_tpcs_sm_pm_ctrl_r());
-        data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(),
-                gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f());
-        data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(),
-                gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f());
-        gk20a_writel(g, gr_gpcs_tpcs_sm_pm_ctrl_r(), data);
-
-        data = gk20a_readl(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r());
-        data = set_field(data, gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(),
-                gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f());
-        gk20a_writel(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r(), data);
-
-        data = gk20a_readl(g, gr_gpcs_tpcs_sm_debug_sfe_control_r());
-        data = set_field(data, gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(),
-                gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f());
-        gk20a_writel(g, gr_gpcs_tpcs_sm_debug_sfe_control_r(), data);
-
-        gk20a_writel(g, therm_peakpower_config6_r(0),
-                therm_peakpower_config6_trigger_cfg_1h_intr_f() |
-                therm_peakpower_config6_trigger_cfg_1l_intr_f());
-
-        gk20a_writel(g, chiplet_pwr_gpcs_config_1_r(),
-                chiplet_pwr_gpcs_config_1_ba_enable_yes_f());
-        gk20a_writel(g, chiplet_pwr_fbps_config_1_r(),
-                chiplet_pwr_fbps_config_1_ba_enable_yes_f());
-
-        data = gk20a_readl(g, therm_config1_r());
-        data = set_field(data, therm_config1_ba_enable_m(),
-                therm_config1_ba_enable_yes_f());
-        gk20a_writel(g, therm_config1_r(), data);
-
-        gk20a_writel(g, gr_gpcs_tpcs_sm_power_throttle_r(), 0x441a);
-
-        gk20a_writel(g, therm_weight_1_r(), 0xd3);
-        gk20a_writel(g, chiplet_pwr_gpcs_weight_6_r(), 0x7d);
-        gk20a_writel(g, chiplet_pwr_gpcs_weight_7_r(), 0xff);
-        gk20a_writel(g, chiplet_pwr_fbps_weight_0_r(), 0x13000000);
-        gk20a_writel(g, chiplet_pwr_fbps_weight_1_r(), 0x19);
-
-        gk20a_writel(g, therm_peakpower_config8_r(0), 0x8);
-        gk20a_writel(g, therm_peakpower_config9_r(0), 0x0);
-
-        gk20a_writel(g, therm_evt_ba_w0_t1h_r(), 0x100);
-
-        gk20a_writel(g, therm_use_a_r(), therm_use_a_ba_w0_t1h_yes_f());
-
-        gk20a_writel(g, therm_peakpower_config1_r(0),
-                therm_peakpower_config1_window_period_2m_f() |
-                therm_peakpower_config1_ba_sum_shift_20_f() |
-                therm_peakpower_config1_window_en_enabled_f());
-
-        gk20a_writel(g, therm_peakpower_config2_r(0),
-                therm_peakpower_config2_ba_threshold_1h_val_f(1) |
-                therm_peakpower_config2_ba_threshold_1h_en_enabled_f());
-
-        gk20a_writel(g, therm_peakpower_config4_r(0),
-                therm_peakpower_config4_ba_threshold_1l_val_f(1) |
-                therm_peakpower_config4_ba_threshold_1l_en_enabled_f());
-*/
         return 0;
 }