gpu: nvgpu: Add bus HAL

Add bus HAL and move all bus related hardware sequencing to that file:
BAR1 binding, timer access, and interrupt handling.

Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323353
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

9 files changed, 204 insertions, 133 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
new file mode 100644
index 00000000..fda1f80e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/tegra/chip-id.h>
+
+#include <nvgpu/page_allocator.h>
+
+#include "gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
+
+void gk20a_bus_init_hw(struct gk20a *g)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+
+        /* enable pri timeout only on silicon */
+        if (tegra_platform_is_silicon()) {
+                gk20a_writel(g,
+                        timer_pri_timeout_r(),
+                        timer_pri_timeout_period_f(
+                                platform->default_pri_timeout ?
+                                        platform->default_pri_timeout :
+                                                                0x186A0) |
+                        timer_pri_timeout_en_en_enabled_f());
+        } else {
+                gk20a_writel(g,
+                        timer_pri_timeout_r(),
+                        timer_pri_timeout_period_f(0x186A0) |
+                        timer_pri_timeout_en_en_disabled_f());
+        }
+
+        if (!tegra_platform_is_silicon())
+                gk20a_writel(g, bus_intr_en_0_r(), 0x0);
+        else
+                gk20a_writel(g, bus_intr_en_0_r(),
+                                bus_intr_en_0_pri_squash_m() |
+                                bus_intr_en_0_pri_fecserr_m() |
+                                bus_intr_en_0_pri_timeout_m());
+}
+
+void gk20a_bus_isr(struct gk20a *g)
+{
+        u32 val, err_code;
+        val = gk20a_readl(g, bus_intr_0_r());
+        if (val & (bus_intr_0_pri_squash_m() |
+                        bus_intr_0_pri_fecserr_m() |
+                        bus_intr_0_pri_timeout_m())) {
+                gk20a_dbg(gpu_dbg_intr, "pmc_enable : 0x%x",
+                        gk20a_readl(g, mc_enable_r()));
+                gk20a_dbg(gpu_dbg_intr, "NV_PBUS_INTR_0 : 0x%x", val);
+                gk20a_dbg(gpu_dbg_intr,
+                        "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n",
+                        gk20a_readl(g, timer_pri_timeout_save_0_r()));
+                gk20a_dbg(gpu_dbg_intr,
+                        "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n",
+                        gk20a_readl(g, timer_pri_timeout_save_1_r()));
+                err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r());
+                gk20a_dbg(gpu_dbg_intr,
+                        "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n",
+                        err_code);
+                if (err_code == 0xbadf13)
+                        gk20a_dbg(gpu_dbg_intr,
+                        "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
+                        gk20a_readl(g, gr_gpc0_fs_gpc_r()));
+
+                gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
+                gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
+        }
+
+        if (val)
+                gk20a_dbg(gpu_dbg_intr,
+                        "Unhandled pending pbus interrupt\n");
+
+        gk20a_writel(g, bus_intr_0_r(), val);
+}
+
+int gk20a_read_ptimer(struct gk20a *g, u64 *value)
+{
+        const unsigned int max_iterations = 3;
+        unsigned int i = 0;
+        u32 gpu_timestamp_hi_prev = 0;
+
+        if (!value)
+                return -EINVAL;
+
+        /* Note. The GPU nanosecond timer consists of two 32-bit
+         * registers (high & low). To detect a possible low register
+         * wrap-around between the reads, we need to read the high
+         * register before and after low. The wraparound happens
+         * approximately once per 4 secs. */
+
+        /* get initial gpu_timestamp_hi value */
+        gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
+
+        for (i = 0; i < max_iterations; ++i) {
+                u32 gpu_timestamp_hi = 0;
+                u32 gpu_timestamp_lo = 0;
+
+                gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
+                gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
+
+                if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
+                        *value = (((u64)gpu_timestamp_hi) << 32) |
+                                gpu_timestamp_lo;
+                        return 0;
+                }
+
+                /* wrap-around detected, retry */
+                gpu_timestamp_hi_prev = gpu_timestamp_hi;
+        }
+
+        /* too many iterations, bail out */
+        gk20a_err(dev_from_gk20a(g), "failed to read ptimer");
+        return -EBUSY;
+}
+
+static int gk20a_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
+{
+        u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
+        u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
+
+        gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
+
+        gk20a_writel(g, bus_bar1_block_r(),
+                     gk20a_aperture_mask(g, bar1_inst,
+                       bus_bar1_block_target_sys_mem_ncoh_f(),
+                       bus_bar1_block_target_vid_mem_f()) |
+                     bus_bar1_block_mode_virtual_f() |
+                     bus_bar1_block_ptr_f(ptr_v));
+
+        return 0;
+}
+
+void gk20a_init_bus(struct gpu_ops *gops)
+{
+        gops->bus.init_hw = gk20a_bus_init_hw;
+        gops->bus.isr = gk20a_bus_isr;
+        gops->bus.read_ptimer = gk20a_read_ptimer;
+        gops->bus.bar1_bind = gk20a_bus_bar1_bind;
+}
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.h b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h
new file mode 100644
index 00000000..01526f06
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef BUS_GK20A_H
+#define BUS_GK20A_H
+
+struct gk20a;
+struct gpu_ops;
+struct mem_desc;
+
+void gk20a_init_bus(struct gpu_ops *gops);
+
+void gk20a_bus_isr(struct gk20a *g);
+int gk20a_read_ptimer(struct gk20a *g, u64 *value);
+void gk20a_bus_init_hw(struct gk20a *g);
+
+#endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
index e6626c4a..67971369 100644
--- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
@@ -725,7 +725,7 @@ static int nvgpu_gpu_get_gpu_time(
         if (err)
                 return err;
 
-        err = g->ops.read_ptimer(g, &time);
+        err = g->ops.bus.read_ptimer(g, &time);
         if (!err)
                 args->gpu_timestamp = time;
 
diff --git a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c
index 4ad2abd6..0736a03b 100644
--- a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c
@@ -686,7 +686,7 @@ void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch)
         if (!g->ctxsw_trace)
                 return;
 
-        g->ops.read_ptimer(g, &entry.timestamp);
+        g->ops.bus.read_ptimer(g, &entry.timestamp);
         gk20a_ctxsw_trace_write(g, &entry);
         gk20a_ctxsw_trace_wake_up(g, 0);
 #endif
@@ -706,7 +706,7 @@ void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg)
         if (!g->ctxsw_trace)
                 return;
 
-        g->ops.read_ptimer(g, &entry.timestamp);
+        g->ops.bus.read_ptimer(g, &entry.timestamp);
         gk20a_ctxsw_trace_write(g, &entry);
         gk20a_ctxsw_trace_wake_up(g, 0);
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 76484dd5..72528758 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -57,6 +57,7 @@
 #include "hal.h"
 #include "vgpu/vgpu.h"
 #include "pci.h"
+#include "bus_gk20a.h"
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "pstate/pstate.h"
 #endif
@@ -70,11 +71,8 @@
 #endif
 
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
 
 
@@ -330,42 +328,6 @@ static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id)
         return g->ops.mc.isr_nonstall(g);
 }
 
-void gk20a_pbus_isr(struct gk20a *g)
-{
-        u32 val, err_code;
-        val = gk20a_readl(g, bus_intr_0_r());
-        if (val & (bus_intr_0_pri_squash_m() |
-                        bus_intr_0_pri_fecserr_m() |
-                        bus_intr_0_pri_timeout_m())) {
-                gk20a_dbg(gpu_dbg_intr, "pmc_enable : 0x%x",
-                        gk20a_readl(g, mc_enable_r()));
-                gk20a_dbg(gpu_dbg_intr, "NV_PBUS_INTR_0 : 0x%x", val);
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n",
-                        gk20a_readl(g, timer_pri_timeout_save_0_r()));
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n",
-                        gk20a_readl(g, timer_pri_timeout_save_1_r()));
-                err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r());
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n",
-                        err_code);
-                if (err_code == 0xbadf13)
-                        gk20a_dbg(gpu_dbg_intr,
-                        "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
-                        gk20a_readl(g, gr_gpc0_fs_gpc_r()));
-
-                gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
-                gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
-        }
-
-        if (val)
-                gk20a_dbg(gpu_dbg_intr,
-                        "Unhandled pending pbus interrupt\n");
-
-        gk20a_writel(g, bus_intr_0_r(), val);
-}
-
 static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id)
 {
         struct gk20a *g = dev_id;
@@ -596,13 +558,7 @@ int gk20a_pm_finalize_poweron(struct device *dev)
         if (err)
                 goto done;
 
-        if (!tegra_platform_is_silicon())
-                gk20a_writel(g, bus_intr_en_0_r(), 0x0);
-        else
-                gk20a_writel(g, bus_intr_en_0_r(),
-                                bus_intr_en_0_pri_squash_m() |
-                                bus_intr_en_0_pri_fecserr_m() |
-                                bus_intr_en_0_pri_timeout_m());
+        g->ops.bus.init_hw(g);
 
         if (g->ops.clk.disable_slowboot)
                 g->ops.clk.disable_slowboot(g);
@@ -630,22 +586,6 @@ int gk20a_pm_finalize_poweron(struct device *dev)
                 }
         }
 
-        /* enable pri timeout only on silicon */
-        if (tegra_platform_is_silicon()) {
-                gk20a_writel(g,
-                        timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(
-                                platform->default_pri_timeout ?
-                                        platform->default_pri_timeout :
-                                                                0x186A0) |
-                        timer_pri_timeout_en_en_enabled_f());
-        } else {
-                gk20a_writel(g,
-                        timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(0x186A0) |
-                        timer_pri_timeout_en_en_disabled_f());
-        }
-
         err = gk20a_init_fifo_reset_enable_hw(g);
         if (err) {
                 gk20a_err(dev, "failed to reset gk20a fifo");
@@ -1910,46 +1850,6 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
         return 0;
 }
 
-int gk20a_read_ptimer(struct gk20a *g, u64 *value)
-{
-        const unsigned int max_iterations = 3;
-        unsigned int i = 0;
-        u32 gpu_timestamp_hi_prev = 0;
-
-        if (!value)
-                return -EINVAL;
-
-        /* Note. The GPU nanosecond timer consists of two 32-bit
-         * registers (high & low). To detect a possible low register
-         * wrap-around between the reads, we need to read the high
-         * register before and after low. The wraparound happens
-         * approximately once per 4 secs. */
-
-        /* get initial gpu_timestamp_hi value */
-        gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
-
-        for (i = 0; i < max_iterations; ++i) {
-                u32 gpu_timestamp_hi = 0;
-                u32 gpu_timestamp_lo = 0;
-
-                gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
-                gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
-
-                if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
-                        *value = (((u64)gpu_timestamp_hi) << 32) |
-                                gpu_timestamp_lo;
-                        return 0;
-                }
-
-                /* wrap-around detected, retry */
-                gpu_timestamp_hi_prev = gpu_timestamp_hi;
-        }
-
-        /* too many iterations, bail out */
-        gk20a_err(dev_from_gk20a(g), "failed to read ptimer");
-        return -EBUSY;
-}
-
 /*
  * Free the gk20a struct.
  */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7c836b3c..8d03cc9a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -629,7 +629,6 @@ struct gpu_ops {
                                 struct vm_gk20a *vm);
                 u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl,
                                          u32 flags);
-                int (*bar1_bind)(struct gk20a *g, struct mem_desc *bar1_inst);
                 size_t (*get_vidmem_size)(struct gk20a *g);
                 void (*init_inst_block)(struct mem_desc *inst_block,
                                 struct vm_gk20a *vm, u32 big_page_size);
@@ -773,7 +772,13 @@ struct gpu_ops {
 
         int (*get_litter_value)(struct gk20a *g, int value);
         int (*chip_init_gpu_characteristics)(struct gk20a *g);
-        int (*read_ptimer)(struct gk20a *g, u64 *value);
+
+        struct {
+                void (*init_hw)(struct gk20a *g);
+                void (*isr)(struct gk20a *g);
+                int (*read_ptimer)(struct gk20a *g, u64 *value);
+                int (*bar1_bind)(struct gk20a *g, struct mem_desc *bar1_inst);
+        } bus;
 
         int (*bios_init)(struct gk20a *g);
 
@@ -1417,8 +1422,6 @@ int gk20a_wait_for_idle(struct device *dev);
 
 int gk20a_init_gpu_characteristics(struct gk20a *g);
 
-void gk20a_pbus_isr(struct gk20a *g);
-
 int gk20a_user_init(struct device *dev, const char *interface_name,
                     struct class *class);
 void gk20a_user_deinit(struct device *dev, struct class *class);
@@ -1435,7 +1438,6 @@ static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
                 return (timeout * 10) / scale10x;
 }
 
-int gk20a_read_ptimer(struct gk20a *g, u64 *value);
 extern struct class nvgpu_class;
 
 #define INTERFACE_NAME "nvhost%s-gpu"
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
index 23725b8b..1e4fffdc 100644
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
@@ -16,6 +16,7 @@
  */
 
 #include "hal_gk20a.h"
+#include "bus_gk20a.h"
 #include "ltc_gk20a.h"
 #include "fb_gk20a.h"
 #include "gk20a.h"
@@ -147,6 +148,7 @@ int gk20a_init_hal(struct gk20a *g)
         gops->privsecurity = 0;
         gops->securegpccs = 0;
         gops->pmupstate = false;
+        gk20a_init_bus(gops);
         gk20a_init_mc(gops);
         gk20a_init_ltc(gops);
         gk20a_init_gr_ops(gops);
@@ -169,7 +171,6 @@ int gk20a_init_hal(struct gk20a *g)
         gops->name = "gk20a";
         gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
         gops->get_litter_value = gk20a_get_litter_value;
-        gops->read_ptimer = gk20a_read_ptimer;
 
         c->twod_class = FERMI_TWOD_A;
         c->threed_class = KEPLER_C;
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index a1861b0d..e51c4a29 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -150,7 +150,7 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
         if (mc_intr_0 & mc_intr_0_ltc_pending_f())
                 g->ops.ltc.isr(g);
         if (mc_intr_0 & mc_intr_0_pbus_pending_f())
-                gk20a_pbus_isr(g);
+                g->ops.bus.isr(g);
 
         /* sync handled irq counter before re-enabling interrupts */
         atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index eaf8f74a..b9217c2c 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -42,12 +42,13 @@
 #include "mm_gk20a.h"
 #include "fence_gk20a.h"
 #include "kind_gk20a.h"
+#include "bus_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 
@@ -1087,8 +1088,8 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
 
         g->ops.fb.init_hw(g);
 
-        if (g->ops.mm.bar1_bind)
-                g->ops.mm.bar1_bind(g, &mm->bar1.inst_block);
+        if (g->ops.bus.bar1_bind)
+                g->ops.bus.bar1_bind(g, &mm->bar1.inst_block);
 
         if (g->ops.mm.init_bar2_mm_hw_setup) {
                 err = g->ops.mm.init_bar2_mm_hw_setup(g);
@@ -1103,23 +1104,6 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
         return 0;
 }
 
-static int gk20a_mm_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
-{
-        u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
-        u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
-
-        gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
-
-        gk20a_writel(g, bus_bar1_block_r(),
-                     gk20a_aperture_mask(g, bar1_inst,
-                       bus_bar1_block_target_sys_mem_ncoh_f(),
-                       bus_bar1_block_target_vid_mem_f()) |
-                     bus_bar1_block_mode_virtual_f() |
-                     bus_bar1_block_ptr_f(ptr_v));
-
-        return 0;
-}
-
 int gk20a_init_mm_support(struct gk20a *g)
 {
         u32 err;
@@ -5447,7 +5431,6 @@ void gk20a_init_mm(struct gpu_ops *gops)
         gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
         gops->mm.init_pdb = gk20a_mm_init_pdb;
         gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
-        gops->mm.bar1_bind = gk20a_mm_bar1_bind;
         gops->mm.init_inst_block = gk20a_init_inst_block;
         gops->mm.is_bar1_supported = gk20a_mm_is_bar1_supported;
         gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;