gpu: nvgpu: add broadcast address decode support for volta

With Volta we have more number of broadcast registers than previous chips
and we don't decode them right now in gr_gk20a_decode_priv_addr()

Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all
previous chips
Add and use gr_gv11b_decode_priv_addr() for Volta

gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set
the broadcast flags apporiately

Define below new broadcast types
PRI_BROADCAST_FLAGS_PMMGPC
PRI_BROADCAST_FLAGS_PMM_GPCS
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA
PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB
PRI_BROADCAST_FLAGS_PMMFBP
PRI_BROADCAST_FLAGS_PMM_FBPS
PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC
PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP

Bug 200398811
Jira NVGPU-556

Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690026
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 33 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index efb425c2..164668cb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -461,6 +461,11 @@ struct gpu_ops {
                                         struct aiv_list_gk20a *regs,
                                         u32 *count, u32 *offset,
                                         u32 max_cnt, u32 base, u32 mask);
+                int (*decode_priv_addr)(struct gk20a *g, u32 addr,
+                              int *addr_type,
+                              u32 *gpc_num, u32 *tpc_num,
+                              u32 *ppc_num, u32 *be_num,
+                              u32 *broadcast_flags);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 65144cc5..3912a1df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6247,7 +6247,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
                                                   u32 *priv_offset);
 
 /* This function will decode a priv address and return the partition type and numbers. */
-static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
+int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
                               int  *addr_type, /* enum ctxsw_addr_type */
                               u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
                               u32 *broadcast_flags)
@@ -6365,7 +6365,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g,
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
-        err = gr_gk20a_decode_priv_addr(g, addr, &addr_type,
+        err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
                                         &gpc_num, &tpc_num, &ppc_num, &be_num,
                                         &broadcast_flags);
         gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type);
@@ -7211,7 +7211,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
 
-        err = gr_gk20a_decode_priv_addr(g, addr, &addr_type,
+        err = g->ops.gr.decode_priv_addr(g, addr, &addr_type,
                                         &gpc_num, &tpc_num, &ppc_num, &be_num,
                                         &broadcast_flags);
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index a80116b7..ee76148a 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -821,4 +821,8 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map,
         struct aiv_list_gk20a *regs,
         u32 *count, u32 *offset,
         u32 max_cnt, u32 base, u32 mask);
+int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
+        int *addr_type,
+        u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
+        u32 *broadcast_flags);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
index d0b6df47..af390833 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Context Pri Register Addressing
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -245,17 +245,27 @@ enum ctxsw_addr_type {
         CTXSW_ADDR_TYPE_FBPA = 6,
         CTXSW_ADDR_TYPE_EGPC = 7,
         CTXSW_ADDR_TYPE_ETPC = 8,
+        CTXSW_ADDR_TYPE_ROP  = 9,
+        CTXSW_ADDR_TYPE_FBP  = 10,
 };
 
-#define PRI_BROADCAST_FLAGS_NONE  0
-#define PRI_BROADCAST_FLAGS_GPC   BIT(0)
-#define PRI_BROADCAST_FLAGS_TPC   BIT(1)
-#define PRI_BROADCAST_FLAGS_BE    BIT(2)
-#define PRI_BROADCAST_FLAGS_PPC   BIT(3)
-#define PRI_BROADCAST_FLAGS_LTCS  BIT(4)
-#define PRI_BROADCAST_FLAGS_LTSS  BIT(5)
-#define PRI_BROADCAST_FLAGS_FBPA  BIT(6)
-#define PRI_BROADCAST_FLAGS_EGPC  BIT(7)
-#define PRI_BROADCAST_FLAGS_ETPC  BIT(8)
+#define PRI_BROADCAST_FLAGS_NONE                0
+#define PRI_BROADCAST_FLAGS_GPC                 BIT(0)
+#define PRI_BROADCAST_FLAGS_TPC                 BIT(1)
+#define PRI_BROADCAST_FLAGS_BE                  BIT(2)
+#define PRI_BROADCAST_FLAGS_PPC                 BIT(3)
+#define PRI_BROADCAST_FLAGS_LTCS                BIT(4)
+#define PRI_BROADCAST_FLAGS_LTSS                BIT(5)
+#define PRI_BROADCAST_FLAGS_FBPA                BIT(6)
+#define PRI_BROADCAST_FLAGS_EGPC                BIT(7)
+#define PRI_BROADCAST_FLAGS_ETPC                BIT(8)
+#define PRI_BROADCAST_FLAGS_PMMGPC              BIT(9)
+#define PRI_BROADCAST_FLAGS_PMM_GPCS            BIT(10)
+#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA   BIT(11)
+#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB   BIT(12)
+#define PRI_BROADCAST_FLAGS_PMMFBP              BIT(13)
+#define PRI_BROADCAST_FLAGS_PMM_FBPS            BIT(14)
+#define PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC       BIT(15)
+#define PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP       BIT(16)
 
 #endif /* GR_PRI_GK20A_H */