diff options
author | Alex Waterman <alexw@nvidia.com> | 2018-03-06 13:43:16 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-07 21:04:41 -0500 |
commit | 418f31cd91a5c3ca45f0920ed64205def49c8a80 (patch) | |
tree | 17e3e04065679788aeeff645842866df0d59ccd0 /drivers/gpu/nvgpu/gk20a | |
parent | f85a0d3e00b53453f3d5ca556f15465078473f31 (diff) |
gpu: nvgpu: Enable IO coherency on GV100
This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434.
This is a revert of a revert, etc, etc. It re-enables IO coherence again.
JIRA EVLR-2333
Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669722
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pramin_gk20a.c | 1 |
7 files changed, 55 insertions, 35 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index 7f0cfe58..b2800772 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -21,6 +21,7 @@ | |||
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <nvgpu/page_allocator.h> | 23 | #include <nvgpu/page_allocator.h> |
24 | #include <nvgpu/enabled.h> | ||
24 | #include <nvgpu/log.h> | 25 | #include <nvgpu/log.h> |
25 | #include <nvgpu/soc.h> | 26 | #include <nvgpu/soc.h> |
26 | #include <nvgpu/bus.h> | 27 | #include <nvgpu/bus.h> |
@@ -155,8 +156,9 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
155 | 156 | ||
156 | gk20a_writel(g, bus_bar1_block_r(), | 157 | gk20a_writel(g, bus_bar1_block_r(), |
157 | nvgpu_aperture_mask(g, bar1_inst, | 158 | nvgpu_aperture_mask(g, bar1_inst, |
158 | bus_bar1_block_target_sys_mem_ncoh_f(), | 159 | bus_bar1_block_target_sys_mem_ncoh_f(), |
159 | bus_bar1_block_target_vid_mem_f()) | | 160 | bus_bar1_block_target_sys_mem_coh_f(), |
161 | bus_bar1_block_target_vid_mem_f()) | | ||
160 | bus_bar1_block_mode_virtual_f() | | 162 | bus_bar1_block_mode_virtual_f() | |
161 | bus_bar1_block_ptr_f(ptr_v)); | 163 | bus_bar1_block_ptr_f(ptr_v)); |
162 | 164 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index a5a2cb51..e3052701 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -98,8 +98,9 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) | |||
98 | gk20a_writel(g, fb_mmu_invalidate_pdb_r(), | 98 | gk20a_writel(g, fb_mmu_invalidate_pdb_r(), |
99 | fb_mmu_invalidate_pdb_addr_f(addr_lo) | | 99 | fb_mmu_invalidate_pdb_addr_f(addr_lo) | |
100 | nvgpu_aperture_mask(g, pdb, | 100 | nvgpu_aperture_mask(g, pdb, |
101 | fb_mmu_invalidate_pdb_aperture_sys_mem_f(), | 101 | fb_mmu_invalidate_pdb_aperture_sys_mem_f(), |
102 | fb_mmu_invalidate_pdb_aperture_vid_mem_f())); | 102 | fb_mmu_invalidate_pdb_aperture_sys_mem_f(), |
103 | fb_mmu_invalidate_pdb_aperture_vid_mem_f())); | ||
103 | 104 | ||
104 | gk20a_writel(g, fb_mmu_invalidate_r(), | 105 | gk20a_writel(g, fb_mmu_invalidate_r(), |
105 | fb_mmu_invalidate_all_va_true_f() | | 106 | fb_mmu_invalidate_all_va_true_f() | |
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 409661fc..4fda0d2e 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -653,6 +653,7 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
653 | return -ENOMEM; | 653 | return -ENOMEM; |
654 | aperture = nvgpu_aperture_mask(g, &trace->trace_buf, | 654 | aperture = nvgpu_aperture_mask(g, &trace->trace_buf, |
655 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(), | 655 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(), |
656 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(), | ||
656 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()); | 657 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()); |
657 | 658 | ||
658 | if (nvgpu_mem_begin(g, mem)) | 659 | if (nvgpu_mem_begin(g, mem)) |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index e12576d2..258006f9 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/dma.h> | 28 | #include <nvgpu/dma.h> |
29 | #include <nvgpu/timers.h> | 29 | #include <nvgpu/timers.h> |
30 | #include <nvgpu/semaphore.h> | 30 | #include <nvgpu/semaphore.h> |
31 | #include <nvgpu/enabled.h> | ||
31 | #include <nvgpu/kmem.h> | 32 | #include <nvgpu/kmem.h> |
32 | #include <nvgpu/log.h> | 33 | #include <nvgpu/log.h> |
33 | #include <nvgpu/soc.h> | 34 | #include <nvgpu/soc.h> |
@@ -666,11 +667,13 @@ static void fifo_engine_exception_status(struct gk20a *g, | |||
666 | static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | 667 | static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) |
667 | { | 668 | { |
668 | struct fifo_runlist_info_gk20a *runlist; | 669 | struct fifo_runlist_info_gk20a *runlist; |
670 | struct fifo_engine_info_gk20a *engine_info; | ||
669 | unsigned int runlist_id; | 671 | unsigned int runlist_id; |
670 | u32 i; | 672 | u32 i; |
671 | size_t runlist_size; | 673 | size_t runlist_size; |
672 | u32 active_engine_id, pbdma_id, engine_id; | 674 | u32 active_engine_id, pbdma_id, engine_id; |
673 | struct fifo_engine_info_gk20a *engine_info; | 675 | int flags = nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ? |
676 | NVGPU_DMA_FORCE_CONTIGUOUS : 0; | ||
674 | 677 | ||
675 | nvgpu_log_fn(g, " "); | 678 | nvgpu_log_fn(g, " "); |
676 | 679 | ||
@@ -705,8 +708,9 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
705 | f->num_runlist_entries, runlist_size); | 708 | f->num_runlist_entries, runlist_size); |
706 | 709 | ||
707 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { | 710 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { |
708 | int err = nvgpu_dma_alloc_sys(g, runlist_size, | 711 | int err = nvgpu_dma_alloc_flags_sys(g, flags, |
709 | &runlist->mem[i]); | 712 | runlist_size, |
713 | &runlist->mem[i]); | ||
710 | if (err) { | 714 | if (err) { |
711 | nvgpu_err(g, "memory allocation failed"); | 715 | nvgpu_err(g, "memory allocation failed"); |
712 | goto clean_up_runlist; | 716 | goto clean_up_runlist; |
@@ -3240,8 +3244,9 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3240 | gk20a_writel(g, fifo_runlist_base_r(), | 3244 | gk20a_writel(g, fifo_runlist_base_r(), |
3241 | fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | | 3245 | fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | |
3242 | nvgpu_aperture_mask(g, &runlist->mem[new_buf], | 3246 | nvgpu_aperture_mask(g, &runlist->mem[new_buf], |
3243 | fifo_runlist_base_target_sys_mem_ncoh_f(), | 3247 | fifo_runlist_base_target_sys_mem_ncoh_f(), |
3244 | fifo_runlist_base_target_vid_mem_f())); | 3248 | fifo_runlist_base_target_sys_mem_coh_f(), |
3249 | fifo_runlist_base_target_vid_mem_f())); | ||
3245 | } | 3250 | } |
3246 | 3251 | ||
3247 | gk20a_writel(g, fifo_runlist_r(), | 3252 | gk20a_writel(g, fifo_runlist_r(), |
@@ -3763,8 +3768,9 @@ static int gk20a_fifo_commit_userd(struct channel_gk20a *c) | |||
3763 | nvgpu_mem_wr32(g, &c->inst_block, | 3768 | nvgpu_mem_wr32(g, &c->inst_block, |
3764 | ram_in_ramfc_w() + ram_fc_userd_w(), | 3769 | ram_in_ramfc_w() + ram_fc_userd_w(), |
3765 | nvgpu_aperture_mask(g, &g->fifo.userd, | 3770 | nvgpu_aperture_mask(g, &g->fifo.userd, |
3766 | pbdma_userd_target_sys_mem_ncoh_f(), | 3771 | pbdma_userd_target_sys_mem_ncoh_f(), |
3767 | pbdma_userd_target_vid_mem_f()) | | 3772 | pbdma_userd_target_sys_mem_coh_f(), |
3773 | pbdma_userd_target_vid_mem_f()) | | ||
3768 | pbdma_userd_addr_f(addr_lo)); | 3774 | pbdma_userd_addr_f(addr_lo)); |
3769 | 3775 | ||
3770 | nvgpu_mem_wr32(g, &c->inst_block, | 3776 | nvgpu_mem_wr32(g, &c->inst_block, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 8b07619d..61975106 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -742,13 +742,14 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, | |||
742 | 742 | ||
743 | static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) | 743 | static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) |
744 | { | 744 | { |
745 | u32 ptr = u64_lo32(nvgpu_inst_block_addr(g, inst_block) | 745 | u64 ptr = nvgpu_inst_block_addr(g, inst_block) >> |
746 | >> ram_in_base_shift_v()); | 746 | ram_in_base_shift_v(); |
747 | u32 aperture = nvgpu_aperture_mask(g, inst_block, | 747 | u32 aperture = nvgpu_aperture_mask(g, inst_block, |
748 | gr_fecs_current_ctx_target_sys_mem_ncoh_f(), | 748 | gr_fecs_current_ctx_target_sys_mem_ncoh_f(), |
749 | gr_fecs_current_ctx_target_vid_mem_f()); | 749 | gr_fecs_current_ctx_target_sys_mem_coh_f(), |
750 | gr_fecs_current_ctx_target_vid_mem_f()); | ||
750 | 751 | ||
751 | return gr_fecs_current_ctx_ptr_f(ptr) | aperture | | 752 | return gr_fecs_current_ctx_ptr_f(u64_lo32(ptr)) | aperture | |
752 | gr_fecs_current_ctx_valid_f(1); | 753 | gr_fecs_current_ctx_valid_f(1); |
753 | } | 754 | } |
754 | 755 | ||
@@ -2199,16 +2200,18 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2199 | 2200 | ||
2200 | inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc); | 2201 | inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc); |
2201 | gk20a_writel(g, gr_fecs_new_ctx_r(), | 2202 | gk20a_writel(g, gr_fecs_new_ctx_r(), |
2202 | gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | | 2203 | gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | |
2203 | nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, | 2204 | nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, |
2204 | gr_fecs_new_ctx_target_sys_mem_ncoh_f(), | 2205 | gr_fecs_new_ctx_target_sys_mem_ncoh_f(), |
2206 | gr_fecs_new_ctx_target_sys_mem_coh_f(), | ||
2205 | gr_fecs_new_ctx_target_vid_mem_f()) | | 2207 | gr_fecs_new_ctx_target_vid_mem_f()) | |
2206 | gr_fecs_new_ctx_valid_m()); | 2208 | gr_fecs_new_ctx_valid_m()); |
2207 | 2209 | ||
2208 | gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), | 2210 | gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), |
2209 | gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | | 2211 | gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | |
2210 | nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, | 2212 | nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, |
2211 | gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), | 2213 | gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), |
2214 | gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(), | ||
2212 | gr_fecs_arb_ctx_ptr_target_vid_mem_f())); | 2215 | gr_fecs_arb_ctx_ptr_target_vid_mem_f())); |
2213 | 2216 | ||
2214 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); | 2217 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); |
@@ -4440,8 +4443,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4440 | 4443 | ||
4441 | gk20a_writel(g, fb_mmu_debug_wr_r(), | 4444 | gk20a_writel(g, fb_mmu_debug_wr_r(), |
4442 | nvgpu_aperture_mask(g, &gr->mmu_wr_mem, | 4445 | nvgpu_aperture_mask(g, &gr->mmu_wr_mem, |
4443 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), | 4446 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), |
4444 | fb_mmu_debug_wr_aperture_vid_mem_f()) | | 4447 | fb_mmu_debug_wr_aperture_sys_mem_coh_f(), |
4448 | fb_mmu_debug_wr_aperture_vid_mem_f()) | | ||
4445 | fb_mmu_debug_wr_vol_false_f() | | 4449 | fb_mmu_debug_wr_vol_false_f() | |
4446 | fb_mmu_debug_wr_addr_f(addr)); | 4450 | fb_mmu_debug_wr_addr_f(addr)); |
4447 | 4451 | ||
@@ -4450,8 +4454,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4450 | 4454 | ||
4451 | gk20a_writel(g, fb_mmu_debug_rd_r(), | 4455 | gk20a_writel(g, fb_mmu_debug_rd_r(), |
4452 | nvgpu_aperture_mask(g, &gr->mmu_rd_mem, | 4456 | nvgpu_aperture_mask(g, &gr->mmu_rd_mem, |
4453 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), | 4457 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), |
4454 | fb_mmu_debug_rd_aperture_vid_mem_f()) | | 4458 | fb_mmu_debug_wr_aperture_sys_mem_coh_f(), |
4459 | fb_mmu_debug_rd_aperture_vid_mem_f()) | | ||
4455 | fb_mmu_debug_rd_vol_false_f() | | 4460 | fb_mmu_debug_rd_vol_false_f() | |
4456 | fb_mmu_debug_rd_addr_f(addr)); | 4461 | fb_mmu_debug_rd_addr_f(addr)); |
4457 | 4462 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index b27d1109..4ff6125b 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -122,8 +122,9 @@ static inline u32 big_valid_pde0_bits(struct gk20a *g, | |||
122 | { | 122 | { |
123 | u32 pde0_bits = | 123 | u32 pde0_bits = |
124 | nvgpu_aperture_mask(g, pd->mem, | 124 | nvgpu_aperture_mask(g, pd->mem, |
125 | gmmu_pde_aperture_big_sys_mem_ncoh_f(), | 125 | gmmu_pde_aperture_big_sys_mem_ncoh_f(), |
126 | gmmu_pde_aperture_big_video_memory_f()) | | 126 | gmmu_pde_aperture_big_sys_mem_coh_f(), |
127 | gmmu_pde_aperture_big_video_memory_f()) | | ||
127 | gmmu_pde_address_big_sys_f( | 128 | gmmu_pde_address_big_sys_f( |
128 | (u32)(addr >> gmmu_pde_address_shift_v())); | 129 | (u32)(addr >> gmmu_pde_address_shift_v())); |
129 | 130 | ||
@@ -135,8 +136,9 @@ static inline u32 small_valid_pde1_bits(struct gk20a *g, | |||
135 | { | 136 | { |
136 | u32 pde1_bits = | 137 | u32 pde1_bits = |
137 | nvgpu_aperture_mask(g, pd->mem, | 138 | nvgpu_aperture_mask(g, pd->mem, |
138 | gmmu_pde_aperture_small_sys_mem_ncoh_f(), | 139 | gmmu_pde_aperture_small_sys_mem_ncoh_f(), |
139 | gmmu_pde_aperture_small_video_memory_f()) | | 140 | gmmu_pde_aperture_small_sys_mem_coh_f(), |
141 | gmmu_pde_aperture_small_video_memory_f()) | | ||
140 | gmmu_pde_vol_small_true_f() | /* tbd: why? */ | 142 | gmmu_pde_vol_small_true_f() | /* tbd: why? */ |
141 | gmmu_pde_address_small_sys_f( | 143 | gmmu_pde_address_small_sys_f( |
142 | (u32)(addr >> gmmu_pde_address_shift_v())); | 144 | (u32)(addr >> gmmu_pde_address_shift_v())); |
@@ -215,6 +217,7 @@ static void __update_pte(struct vm_gk20a *vm, | |||
215 | 217 | ||
216 | pte_w[1] = __nvgpu_aperture_mask(g, attrs->aperture, | 218 | pte_w[1] = __nvgpu_aperture_mask(g, attrs->aperture, |
217 | gmmu_pte_aperture_sys_mem_ncoh_f(), | 219 | gmmu_pte_aperture_sys_mem_ncoh_f(), |
220 | gmmu_pte_aperture_sys_mem_coh_f(), | ||
218 | gmmu_pte_aperture_video_memory_f()) | | 221 | gmmu_pte_aperture_video_memory_f()) | |
219 | gmmu_pte_kind_f(attrs->kind_v) | | 222 | gmmu_pte_kind_f(attrs->kind_v) | |
220 | gmmu_pte_comptagline_f((u32)(attrs->ctag >> ctag_shift)); | 223 | gmmu_pte_comptagline_f((u32)(attrs->ctag >> ctag_shift)); |
@@ -268,7 +271,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm, | |||
268 | page_size >> 10, | 271 | page_size >> 10, |
269 | nvgpu_gmmu_perm_str(attrs->rw_flag), | 272 | nvgpu_gmmu_perm_str(attrs->rw_flag), |
270 | attrs->kind_v, | 273 | attrs->kind_v, |
271 | nvgpu_aperture_str(attrs->aperture), | 274 | nvgpu_aperture_str(g, attrs->aperture), |
272 | attrs->cacheable ? 'C' : '-', | 275 | attrs->cacheable ? 'C' : '-', |
273 | attrs->sparse ? 'S' : '-', | 276 | attrs->sparse ? 'S' : '-', |
274 | attrs->priv ? 'P' : '-', | 277 | attrs->priv ? 'P' : '-', |
@@ -363,11 +366,12 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | |||
363 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); | 366 | gk20a_dbg_info("pde pa=0x%llx", pdb_addr); |
364 | 367 | ||
365 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), | 368 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(), |
366 | nvgpu_aperture_mask(g, vm->pdb.mem, | 369 | nvgpu_aperture_mask(g, vm->pdb.mem, |
367 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), | 370 | ram_in_page_dir_base_target_sys_mem_ncoh_f(), |
368 | ram_in_page_dir_base_target_vid_mem_f()) | | 371 | ram_in_page_dir_base_target_sys_mem_coh_f(), |
369 | ram_in_page_dir_base_vol_true_f() | | 372 | ram_in_page_dir_base_target_vid_mem_f()) | |
370 | ram_in_page_dir_base_lo_f(pdb_addr_lo)); | 373 | ram_in_page_dir_base_vol_true_f() | |
374 | ram_in_page_dir_base_lo_f(pdb_addr_lo)); | ||
371 | 375 | ||
372 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), | 376 | nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(), |
373 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); | 377 | ram_in_page_dir_base_hi_f(pdb_addr_hi)); |
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c index bb8831e0..67fd2480 100644 --- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c | |||
@@ -41,6 +41,7 @@ u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem, | |||
41 | u32 lo = (u32)(addr & 0xfffff); | 41 | u32 lo = (u32)(addr & 0xfffff); |
42 | u32 win = nvgpu_aperture_mask(g, mem, | 42 | u32 win = nvgpu_aperture_mask(g, mem, |
43 | bus_bar0_window_target_sys_mem_noncoherent_f(), | 43 | bus_bar0_window_target_sys_mem_noncoherent_f(), |
44 | bus_bar0_window_target_sys_mem_coherent_f(), | ||
44 | bus_bar0_window_target_vid_mem_f()) | | 45 | bus_bar0_window_target_vid_mem_f()) | |
45 | bus_bar0_window_base_f(hi); | 46 | bus_bar0_window_base_f(hi); |
46 | 47 | ||