diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-15 04:34:59 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-15 11:46:09 -0500 |
commit | 3ff666c4b97c5ad869aefe0d9c335c187962c20e (patch) | |
tree | 42ad94e7e5b877154a482e07746bb45e6a0b0d6c /drivers/gpu/nvgpu/gk20a | |
parent | 592a31fd925d84622602b235647e9b50e2d34f47 (diff) |
gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs
TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using
combination of timeslice and interleave levels to decide the priority
Hence remove the IOCTLs and all corresponding APIs
Jira NVGPU-393
Change-Id: I7cf0785689269536eca0c278c774b0e9e74f8c2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598581
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 23 |
6 files changed, 0 insertions, 63 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 04ee84f4..99c518b5 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -427,7 +427,6 @@ void gk20a_ce_suspend(struct gk20a *g) | |||
427 | /* CE app utility functions */ | 427 | /* CE app utility functions */ |
428 | u32 gk20a_ce_create_context(struct gk20a *g, | 428 | u32 gk20a_ce_create_context(struct gk20a *g, |
429 | int runlist_id, | 429 | int runlist_id, |
430 | int priority, | ||
431 | int timeslice, | 430 | int timeslice, |
432 | int runlist_level) | 431 | int runlist_level) |
433 | { | 432 | { |
@@ -507,16 +506,6 @@ u32 gk20a_ce_create_context(struct gk20a *g, | |||
507 | 506 | ||
508 | memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size); | 507 | memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size); |
509 | 508 | ||
510 | /* -1 means default channel priority */ | ||
511 | if (priority != -1) { | ||
512 | err = gk20a_fifo_set_priority(ce_ctx->ch, priority); | ||
513 | if (err) { | ||
514 | nvgpu_err(g, | ||
515 | "ce: could not set the channel priority for CE context"); | ||
516 | goto end; | ||
517 | } | ||
518 | } | ||
519 | |||
520 | /* -1 means default channel timeslice value */ | 509 | /* -1 means default channel timeslice value */ |
521 | if (timeslice != -1) { | 510 | if (timeslice != -1) { |
522 | err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); | 511 | err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 5c3a1cfc..1d9d8c72 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -128,7 +128,6 @@ void gk20a_ce_destroy(struct gk20a *g); | |||
128 | /* CE app utility functions */ | 128 | /* CE app utility functions */ |
129 | u32 gk20a_ce_create_context(struct gk20a *g, | 129 | u32 gk20a_ce_create_context(struct gk20a *g, |
130 | int runlist_id, | 130 | int runlist_id, |
131 | int priority, | ||
132 | int timeslice, | 131 | int timeslice, |
133 | int runlist_level); | 132 | int runlist_level); |
134 | int gk20a_ce_execute_ops(struct gk20a *g, | 133 | int gk20a_ce_execute_ops(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 1ea7d6b3..648a8c86 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3962,32 +3962,6 @@ int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
3962 | return channel_gk20a_set_schedule_params(ch); | 3962 | return channel_gk20a_set_schedule_params(ch); |
3963 | } | 3963 | } |
3964 | 3964 | ||
3965 | int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority) | ||
3966 | { | ||
3967 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
3968 | nvgpu_err(ch->g, "invalid operation for TSG!"); | ||
3969 | return -EINVAL; | ||
3970 | } | ||
3971 | |||
3972 | /* set priority of graphics channel */ | ||
3973 | switch (priority) { | ||
3974 | case NVGPU_PRIORITY_LOW: | ||
3975 | ch->timeslice_us = ch->g->timeslice_low_priority_us; | ||
3976 | break; | ||
3977 | case NVGPU_PRIORITY_MEDIUM: | ||
3978 | ch->timeslice_us = ch->g->timeslice_medium_priority_us; | ||
3979 | break; | ||
3980 | case NVGPU_PRIORITY_HIGH: | ||
3981 | ch->timeslice_us = ch->g->timeslice_high_priority_us; | ||
3982 | break; | ||
3983 | default: | ||
3984 | pr_err("Unsupported priority"); | ||
3985 | return -EINVAL; | ||
3986 | } | ||
3987 | |||
3988 | return channel_gk20a_set_schedule_params(ch); | ||
3989 | } | ||
3990 | |||
3991 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) | 3965 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) |
3992 | { | 3966 | { |
3993 | struct gk20a *g = c->g; | 3967 | struct gk20a *g = c->g; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index fa1d9f72..3587ffa8 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -383,7 +383,6 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, | |||
383 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | 383 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, |
384 | u64 gpfifo_base, u32 gpfifo_entries, | 384 | u64 gpfifo_base, u32 gpfifo_entries, |
385 | unsigned long timeout, u32 flags); | 385 | unsigned long timeout, u32 flags); |
386 | int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority); | ||
387 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); | 386 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); |
388 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); | 387 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); |
389 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); | 388 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fb12d0d2..3381d974 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -513,7 +513,6 @@ struct gpu_ops { | |||
513 | int (*wait_engine_idle)(struct gk20a *g); | 513 | int (*wait_engine_idle)(struct gk20a *g); |
514 | u32 (*get_num_fifos)(struct gk20a *g); | 514 | u32 (*get_num_fifos)(struct gk20a *g); |
515 | u32 (*get_pbdma_signature)(struct gk20a *g); | 515 | u32 (*get_pbdma_signature)(struct gk20a *g); |
516 | int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority); | ||
517 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, | 516 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, |
518 | bool is_tsg, u32 runlist_id, | 517 | bool is_tsg, u32 runlist_id, |
519 | u32 new_level); | 518 | u32 new_level); |
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 5af01a05..636ee8a0 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -200,29 +200,6 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid) | |||
200 | return 0; | 200 | return 0; |
201 | } | 201 | } |
202 | 202 | ||
203 | int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, | ||
204 | u32 priority) | ||
205 | { | ||
206 | u32 timeslice_us; | ||
207 | |||
208 | switch (priority) { | ||
209 | case NVGPU_PRIORITY_LOW: | ||
210 | timeslice_us = g->timeslice_low_priority_us; | ||
211 | break; | ||
212 | case NVGPU_PRIORITY_MEDIUM: | ||
213 | timeslice_us = g->timeslice_medium_priority_us; | ||
214 | break; | ||
215 | case NVGPU_PRIORITY_HIGH: | ||
216 | timeslice_us = g->timeslice_high_priority_us; | ||
217 | break; | ||
218 | default: | ||
219 | pr_err("Unsupported priority"); | ||
220 | return -EINVAL; | ||
221 | } | ||
222 | |||
223 | return gk20a_tsg_set_timeslice(tsg, timeslice_us); | ||
224 | } | ||
225 | |||
226 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) | 203 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) |
227 | { | 204 | { |
228 | struct gk20a *g = tsg->g; | 205 | struct gk20a *g = tsg->g; |