diff options
author | Peter Daifuku <pdaifuku@nvidia.com> | 2016-06-28 13:34:15 -0400 |
---|---|---|
committer | Peter Daifuku <pdaifuku@nvidia.com> | 2016-07-30 14:29:20 -0400 |
commit | 38a59acc776c8ad5b7b5506d13a60712af7d5318 (patch) | |
tree | 4eeb2d238327e7c84e3915e1c50ae938c2e02b65 /drivers/gpu/nvgpu/gk20a | |
parent | 92415fd36694c6c8dcfbcf1de2e7197d4f883451 (diff) |
gpu: nvgpu: move dbg_session_ops to gops
Move dbg_session_ops to gops for better code consistency
JIRA VFND-1905
Change-Id: I04a11d77dd8c26d9922e80e556822f80dd2bc36d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 3 |
5 files changed, 26 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index de8db2ba..f1f2cc70 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -31,13 +31,6 @@ | |||
31 | #include "hw_gr_gk20a.h" | 31 | #include "hw_gr_gk20a.h" |
32 | #include "hw_perf_gk20a.h" | 32 | #include "hw_perf_gk20a.h" |
33 | 33 | ||
34 | static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, u32 powermode); | ||
35 | |||
36 | struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a = { | ||
37 | .exec_reg_ops = exec_regops_gk20a, | ||
38 | .dbg_set_powergate = dbg_set_powergate, | ||
39 | }; | ||
40 | |||
41 | /* | 34 | /* |
42 | * API to get first channel from the list of all channels | 35 | * API to get first channel from the list of all channels |
43 | * bound to the debug session | 36 | * bound to the debug session |
@@ -84,7 +77,6 @@ static int alloc_session(struct dbg_session_gk20a **_dbg_s) | |||
84 | return -ENOMEM; | 77 | return -ENOMEM; |
85 | 78 | ||
86 | dbg_s->id = generate_session_id(); | 79 | dbg_s->id = generate_session_id(); |
87 | dbg_s->ops = &dbg_gpu_session_ops_gk20a; | ||
88 | *_dbg_s = dbg_s; | 80 | *_dbg_s = dbg_s; |
89 | return 0; | 81 | return 0; |
90 | } | 82 | } |
@@ -478,7 +470,7 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp) | |||
478 | * calling powergate/timeout enable ioctl | 470 | * calling powergate/timeout enable ioctl |
479 | */ | 471 | */ |
480 | mutex_lock(&g->dbg_sessions_lock); | 472 | mutex_lock(&g->dbg_sessions_lock); |
481 | dbg_s->ops->dbg_set_powergate(dbg_s, | 473 | g->ops.dbg_session_ops.dbg_set_powergate(dbg_s, |
482 | NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); | 474 | NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); |
483 | nvgpu_dbg_timeout_enable(dbg_s, NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE); | 475 | nvgpu_dbg_timeout_enable(dbg_s, NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE); |
484 | mutex_unlock(&g->dbg_sessions_lock); | 476 | mutex_unlock(&g->dbg_sessions_lock); |
@@ -976,7 +968,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
976 | 968 | ||
977 | gk20a_dbg_fn("%d ops, total size %llu", args->num_ops, ops_size); | 969 | gk20a_dbg_fn("%d ops, total size %llu", args->num_ops, ops_size); |
978 | 970 | ||
979 | if (!dbg_s->ops) { | 971 | if (!dbg_s->id) { |
980 | gk20a_err(dev, "can't call reg_ops on an unbound debugger session"); | 972 | gk20a_err(dev, "can't call reg_ops on an unbound debugger session"); |
981 | return -EINVAL; | 973 | return -EINVAL; |
982 | } | 974 | } |
@@ -1018,16 +1010,18 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
1018 | /* In the virtual case, the server will handle | 1010 | /* In the virtual case, the server will handle |
1019 | * disabling/enabling powergating when processing reg ops | 1011 | * disabling/enabling powergating when processing reg ops |
1020 | */ | 1012 | */ |
1021 | powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s, | 1013 | powergate_err = g->ops.dbg_session_ops.dbg_set_powergate(dbg_s, |
1022 | NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE); | 1014 | NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE); |
1023 | is_pg_disabled = true; | 1015 | is_pg_disabled = true; |
1024 | } | 1016 | } |
1025 | 1017 | ||
1026 | if (!powergate_err) { | 1018 | if (!powergate_err) { |
1027 | err = dbg_s->ops->exec_reg_ops(dbg_s, ops, args->num_ops); | 1019 | err = g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops, |
1020 | args->num_ops); | ||
1028 | /* enable powergate, if previously disabled */ | 1021 | /* enable powergate, if previously disabled */ |
1029 | if (is_pg_disabled) { | 1022 | if (is_pg_disabled) { |
1030 | powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s, | 1023 | powergate_err = |
1024 | g->ops.dbg_session_ops.dbg_set_powergate(dbg_s, | ||
1031 | NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); | 1025 | NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); |
1032 | } | 1026 | } |
1033 | } | 1027 | } |
@@ -1166,7 +1160,7 @@ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, | |||
1166 | dev_name(dbg_s->dev), args->mode); | 1160 | dev_name(dbg_s->dev), args->mode); |
1167 | 1161 | ||
1168 | mutex_lock(&g->dbg_sessions_lock); | 1162 | mutex_lock(&g->dbg_sessions_lock); |
1169 | err = dbg_s->ops->dbg_set_powergate(dbg_s, args->mode); | 1163 | err = g->ops.dbg_session_ops.dbg_set_powergate(dbg_s, args->mode); |
1170 | mutex_unlock(&g->dbg_sessions_lock); | 1164 | mutex_unlock(&g->dbg_sessions_lock); |
1171 | return err; | 1165 | return err; |
1172 | } | 1166 | } |
@@ -1404,3 +1398,9 @@ static int gk20a_perfbuf_unmap(struct dbg_session_gk20a *dbg_s, | |||
1404 | 1398 | ||
1405 | return 0; | 1399 | return 0; |
1406 | } | 1400 | } |
1401 | |||
1402 | void gk20a_init_dbg_session_ops(struct gpu_ops *gops) | ||
1403 | { | ||
1404 | gops->dbg_session_ops.exec_reg_ops = exec_regops_gk20a; | ||
1405 | gops->dbg_session_ops.dbg_set_powergate = dbg_set_powergate; | ||
1406 | }; | ||
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h index 55ff54b9..600715f5 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h | |||
@@ -34,13 +34,6 @@ void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch); | |||
34 | struct channel_gk20a * | 34 | struct channel_gk20a * |
35 | nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s); | 35 | nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s); |
36 | 36 | ||
37 | struct dbg_gpu_session_ops { | ||
38 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, | ||
39 | struct nvgpu_dbg_gpu_reg_op *ops, | ||
40 | u64 num_ops); | ||
41 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, u32 mode); | ||
42 | }; | ||
43 | |||
44 | struct dbg_gpu_session_events { | 37 | struct dbg_gpu_session_events { |
45 | wait_queue_head_t wait_queue; | 38 | wait_queue_head_t wait_queue; |
46 | bool events_enabled; | 39 | bool events_enabled; |
@@ -76,9 +69,6 @@ struct dbg_session_gk20a { | |||
76 | struct list_head ch_list; | 69 | struct list_head ch_list; |
77 | struct mutex ch_list_lock; | 70 | struct mutex ch_list_lock; |
78 | 71 | ||
79 | /* session operations */ | ||
80 | struct dbg_gpu_session_ops *ops; | ||
81 | |||
82 | /* event support */ | 72 | /* event support */ |
83 | struct dbg_gpu_session_events dbg_events; | 73 | struct dbg_gpu_session_events dbg_events; |
84 | 74 | ||
@@ -98,12 +88,11 @@ struct dbg_session_channel_data { | |||
98 | struct dbg_session_data *session_data; | 88 | struct dbg_session_data *session_data; |
99 | }; | 89 | }; |
100 | 90 | ||
101 | extern struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a; | ||
102 | |||
103 | int dbg_unbind_single_channel_gk20a(struct dbg_session_gk20a *dbg_s, | 91 | int dbg_unbind_single_channel_gk20a(struct dbg_session_gk20a *dbg_s, |
104 | struct dbg_session_channel_data *ch_data); | 92 | struct dbg_session_channel_data *ch_data); |
105 | 93 | ||
106 | bool gk20a_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch); | 94 | bool gk20a_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch); |
107 | int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch); | 95 | int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch); |
96 | void gk20a_init_dbg_session_ops(struct gpu_ops *gops); | ||
108 | 97 | ||
109 | #endif /* DBG_GPU_GK20A_H */ | 98 | #endif /* DBG_GPU_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index cefdccd5..7eb98a2c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -629,6 +629,13 @@ struct gpu_ops { | |||
629 | struct gk20a_debug_output *o); | 629 | struct gk20a_debug_output *o); |
630 | } debug; | 630 | } debug; |
631 | struct { | 631 | struct { |
632 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, | ||
633 | struct nvgpu_dbg_gpu_reg_op *ops, | ||
634 | u64 num_ops); | ||
635 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, | ||
636 | u32 mode); | ||
637 | } dbg_session_ops; | ||
638 | struct { | ||
632 | void (*get_program_numbers)(struct gk20a *g, | 639 | void (*get_program_numbers)(struct gk20a *g, |
633 | u32 block_height_log2, | 640 | u32 block_height_log2, |
634 | int *hprog, int *vprog); | 641 | int *hprog, int *vprog); |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index e0479573..4da7ffad 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "therm_gk20a.h" | 31 | #include "therm_gk20a.h" |
32 | #include "hw_proj_gk20a.h" | 32 | #include "hw_proj_gk20a.h" |
33 | #include "tsg_gk20a.h" | 33 | #include "tsg_gk20a.h" |
34 | #include "dbg_gpu_gk20a.h" | ||
34 | 35 | ||
35 | static struct gpu_ops gk20a_ops = { | 36 | static struct gpu_ops gk20a_ops = { |
36 | .clock_gating = { | 37 | .clock_gating = { |
@@ -153,6 +154,7 @@ int gk20a_init_hal(struct gk20a *g) | |||
153 | gk20a_init_clk_ops(gops); | 154 | gk20a_init_clk_ops(gops); |
154 | gk20a_init_regops(gops); | 155 | gk20a_init_regops(gops); |
155 | gk20a_init_debug_ops(gops); | 156 | gk20a_init_debug_ops(gops); |
157 | gk20a_init_dbg_session_ops(gops); | ||
156 | gk20a_init_therm_ops(gops); | 158 | gk20a_init_therm_ops(gops); |
157 | gk20a_init_tsg_ops(gops); | 159 | gk20a_init_tsg_ops(gops); |
158 | gops->name = "gk20a"; | 160 | gops->name = "gk20a"; |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 6e21e857..8b87b523 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -825,7 +825,8 @@ static int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | |||
825 | ops[3].offset = 0x00419f40; | 825 | ops[3].offset = 0x00419f40; |
826 | ops[3].value_lo = 0x18; | 826 | ops[3].value_lo = 0x18; |
827 | 827 | ||
828 | return dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops)); | 828 | return dbg_s->g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops, |
829 | ARRAY_SIZE(ops)); | ||
829 | } | 830 | } |
830 | 831 | ||
831 | void gk20a_init_regops(struct gpu_ops *gops) | 832 | void gk20a_init_regops(struct gpu_ops *gops) |