gpu: nvgpu: load secure gpccs using dma

bug 200080684

use new cmd defined in ucode for loading
GR falcons. flip PRIV load flag in lsb
header to indicate using dma. use pmu msg
as cmd completion for new cmd instead of
polling fecs mailbox. also move
check for using dma in non secure boot path
to hal.

Change-Id: I22582a705bd1ae0603f858e1fe200d72e6794a81
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/761625
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 31 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d8e3586f..9a183e44 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -333,6 +333,7 @@ struct gpu_ops {
         struct {
                 int (*get_netlist_name)(int index, char *name);
                 bool (*is_fw_defined)(void);
+                bool use_dma_for_fw_bootstrap;
         } gr_ctx;
         struct {
                 bool (*support_sparse)(struct gk20a *g);
@@ -383,7 +384,9 @@ struct gpu_ops {
                 int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
                 int (*pmu_setup_elpg)(struct gk20a *g);
                 int (*init_wpr_region)(struct gk20a *g);
+                int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
                 u32  lspmuwprinitdone;
+                u32  lsfloadedfalconid;
                 bool fecsbootstrapdone;
         } pmu;
         struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
index cd9a9fca..94dba7b6 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
@@ -3,7 +3,7 @@
  *
  * GK20A Graphics Context
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -345,4 +345,5 @@ void gk20a_init_gr_ctx(struct gpu_ops *gops)
 {
         gops->gr_ctx.get_netlist_name = gr_gk20a_get_netlist_name;
         gops->gr_ctx.is_fw_defined = gr_gk20a_is_firmware_defined;
+        gops->gr_ctx.use_dma_for_fw_bootstrap = true;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index edd4c6c8..e232bf17 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2128,7 +2128,7 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g)
          * In case bootloader is not supported, revert to the old way of
          * loading gr ucode, without the faster bootstrap routine.
          */
-        if (g->gpu_characteristics.arch > NVGPU_GPU_ARCH_GM200) {
+        if (!g->ops.gr_ctx.use_dma_for_fw_bootstrap) {
                 gr_gk20a_load_falcon_dmem(g);
                 gr_gk20a_load_falcon_imem(g);
                 gr_gk20a_start_falcon_ucode(g);
@@ -2161,7 +2161,7 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g)
                 return ret;
         }
 
-        if (!(g->gpu_characteristics.arch > NVGPU_GPU_ARCH_GM200))
+        if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || g->ops.securegpccs)
                 gk20a_writel(g, gr_fecs_current_ctx_r(),
                         gr_fecs_current_ctx_valid_false_f());
 
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 11322293..1f21555c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2647,6 +2647,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
         gops->pmu.pmu_setup_elpg = NULL;
         gops->pmu.init_wpr_region = NULL;
+        gops->pmu.load_lsfalcon_ucode = NULL;
 }
 
 int gk20a_init_pmu_support(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index f29c810e..85403767 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -304,6 +304,11 @@ enum {
         GK20A_PMU_DMAIDX_END            = 7
 };
 
+struct falc_u64 {
+        u32 lo;
+        u32 hi;
+};
+
 struct falc_dma_addr {
         u32 dma_base;
         /*dma_base1 is 9-bit MSB for FB Base
@@ -708,6 +713,8 @@ struct pmu_pg_cmd {
 enum {
         PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0          ,
         PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
+        PMU_ACR_CMD_ID_RESERVED,
+        PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
 };
 
 /*
@@ -729,14 +736,27 @@ struct pmu_acr_cmd_bootstrap_falcon {
         u32 falconid;
 };
 
+/*
+ * falcon ID to bootstrap
+ */
+struct pmu_acr_cmd_bootstrap_multiple_falcons {
+        u8 cmd_type;
+        u32 flags;
+        u32 falconidmask;
+        u32 usevamask;
+        struct falc_u64 wprvirtualbase;
+};
+
 #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO  1
 #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
 
+
 struct pmu_acr_cmd {
         union {
                 u8 cmd_type;
                 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
                 struct pmu_acr_cmd_init_wpr_details init_wpr;
+                struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
         };
 };
 
@@ -1177,6 +1197,7 @@ struct pmu_gk20a {
         /* TBD: remove this if ZBC seq is fixed */
         struct mem_desc seq_buf;
         struct mem_desc trace_buf;
+        struct mem_desc wpr_buf;
         bool buf_loaded;
 
         struct pmu_sha1_gid gid_info;
@@ -1294,4 +1315,6 @@ int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
 void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable);
 int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout,
                                  u32 *var, u32 val);
+void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
+                                void *param, u32 handle, u32 status);
 #endif /*__PMU_GK20A_H__*/