diff options
author | Alex Frid <afrid@nvidia.com> | 2014-07-14 20:01:31 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:29 -0400 |
commit | 3058fb2b960cf1da53fd25c5c8d286d60560615e (patch) | |
tree | 6a0b48f79161ed6c272948e6d4834bf7d83976ad /drivers/gpu/nvgpu/gk20a | |
parent | 5ea7ab10ecddc6d6f8d9c72ea6e60ba260389c63 (diff) |
gpu: nvgpu: Use 1kHz resolution for GPCPLL programming
Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming:
limits specifications, calculating GPCPLL settings, storing target
frequency values, and proving output from debug monitor. Updated
comments in clock header to properly reflect frequency units.
Bug 1450787
Change-Id: Ica58f794b82522288f2883c40626d82dbd794902
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437943
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 20 |
2 files changed, 23 insertions, 20 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 151a332b..33d81bd4 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -34,12 +34,12 @@ | |||
34 | 34 | ||
35 | /* from vbios PLL info table */ | 35 | /* from vbios PLL info table */ |
36 | struct pll_parms gpc_pll_params = { | 36 | struct pll_parms gpc_pll_params = { |
37 | 144, 2064, /* freq */ | 37 | 144000, 2064000, /* freq */ |
38 | 1000, 2064, /* vco */ | 38 | 1000000, 2064000, /* vco */ |
39 | 12, 38, /* u */ | 39 | 12000, 38000, /* u */ |
40 | 1, 255, /* M */ | 40 | 1, 255, /* M */ |
41 | 8, 255, /* N */ | 41 | 8, 255, /* N */ |
42 | 1, 32, /* PL */ | 42 | 1, 32, /* PL */ |
43 | }; | 43 | }; |
44 | 44 | ||
45 | static int num_gpu_cooling_freq; | 45 | static int num_gpu_cooling_freq; |
@@ -467,7 +467,7 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
467 | clk->pll_delay = 300; /* usec */ | 467 | clk->pll_delay = 300; /* usec */ |
468 | 468 | ||
469 | clk->gpc_pll.id = GK20A_GPC_PLL; | 469 | clk->gpc_pll.id = GK20A_GPC_PLL; |
470 | clk->gpc_pll.clk_in = ref_rate / 1000000; /* MHz */ | 470 | clk->gpc_pll.clk_in = ref_rate / KHZ; |
471 | 471 | ||
472 | /* Decide initial frequency */ | 472 | /* Decide initial frequency */ |
473 | if (!initialized) { | 473 | if (!initialized) { |
@@ -777,7 +777,7 @@ static int pll_reg_show(struct seq_file *s, void *data) | |||
777 | pl = trim_sys_gpcpll_coeff_pldiv_v(reg); | 777 | pl = trim_sys_gpcpll_coeff_pldiv_v(reg); |
778 | f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div[pl]); | 778 | f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div[pl]); |
779 | seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); | 779 | seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); |
780 | seq_printf(s, " : pll_f(gpu_f) = %u(%u) MHz\n", f, f/2); | 780 | seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2); |
781 | mutex_unlock(&g->clk.clk_mutex); | 781 | mutex_unlock(&g->clk.clk_mutex); |
782 | return 0; | 782 | return 0; |
783 | } | 783 | } |
@@ -801,7 +801,7 @@ static int monitor_get(void *data, u64 *val) | |||
801 | int err; | 801 | int err; |
802 | 802 | ||
803 | u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */ | 803 | u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */ |
804 | u32 clkin = clk->gpc_pll.clk_in; | 804 | u64 freq = clk->gpc_pll.clk_in; |
805 | u32 count1, count2; | 805 | u32 count1, count2; |
806 | 806 | ||
807 | err = gk20a_busy(g->dev); | 807 | err = gk20a_busy(g->dev); |
@@ -824,7 +824,10 @@ static int monitor_get(void *data, u64 *val) | |||
824 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 824 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
825 | udelay(100); | 825 | udelay(100); |
826 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 826 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
827 | *val = (u64)(trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2) * clkin / ncycle); | 827 | freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); |
828 | do_div(freq, ncycle); | ||
829 | *val = freq; | ||
830 | |||
828 | gk20a_idle(g->dev); | 831 | gk20a_idle(g->dev); |
829 | 832 | ||
830 | if (count1 != count2) | 833 | if (count1 != count2) |
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index d2665259..533e6d1e 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -31,18 +31,18 @@ enum { | |||
31 | 31 | ||
32 | struct pll { | 32 | struct pll { |
33 | u32 id; | 33 | u32 id; |
34 | u32 clk_in; /* MHz */ | 34 | u32 clk_in; /* KHz */ |
35 | u32 M; | 35 | u32 M; |
36 | u32 N; | 36 | u32 N; |
37 | u32 PL; | 37 | u32 PL; |
38 | u32 freq; /* MHz */ | 38 | u32 freq; /* KHz */ |
39 | bool enabled; | 39 | bool enabled; |
40 | }; | 40 | }; |
41 | 41 | ||
42 | struct pll_parms { | 42 | struct pll_parms { |
43 | u32 min_freq, max_freq; /* MHz */ | 43 | u32 min_freq, max_freq; /* KHz */ |
44 | u32 min_vco, max_vco; /* MHz */ | 44 | u32 min_vco, max_vco; /* KHz */ |
45 | u32 min_u, max_u; /* MHz */ | 45 | u32 min_u, max_u; /* KHz */ |
46 | u32 min_M, max_M; | 46 | u32 min_M, max_M; |
47 | u32 min_N, max_N; | 47 | u32 min_N, max_N; |
48 | u32 min_PL, max_PL; | 48 | u32 min_PL, max_PL; |
@@ -60,7 +60,7 @@ struct clk_gk20a { | |||
60 | 60 | ||
61 | struct gpufreq_table_data { | 61 | struct gpufreq_table_data { |
62 | unsigned int index; | 62 | unsigned int index; |
63 | unsigned int frequency; /* MHz */ | 63 | unsigned int frequency; /* Hz */ |
64 | }; | 64 | }; |
65 | 65 | ||
66 | struct gpufreq_table_data *tegra_gpufreq_table_get(void); | 66 | struct gpufreq_table_data *tegra_gpufreq_table_get(void); |
@@ -82,13 +82,13 @@ extern struct pll_parms gpc_pll_params; | |||
82 | 82 | ||
83 | static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate) | 83 | static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate) |
84 | { | 84 | { |
85 | /* convert the MHz gpc2clk frequency to Hz gpcpll frequency */ | 85 | /* convert the kHz gpc2clk frequency to Hz gpcpll frequency */ |
86 | return (rate * MHZ) / 2; | 86 | return (rate * KHZ) / 2; |
87 | } | 87 | } |
88 | static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) | 88 | static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) |
89 | { | 89 | { |
90 | /* convert the Hz gpcpll frequency to MHz gpc2clk frequency */ | 90 | /* convert the Hz gpcpll frequency to kHz gpc2clk frequency */ |
91 | return (rate * 2) / MHZ; | 91 | return (rate * 2) / KHZ; |
92 | } | 92 | } |
93 | 93 | ||
94 | #endif /* _NVHOST_CLK_GK20A_H_ */ | 94 | #endif /* _NVHOST_CLK_GK20A_H_ */ |