gpu: nvgpu: changing page_idx from int to u64

page_idx is an element of the struct nvgpu_semaphore_pool, defined in
include/nvgpu/semaphore.h file.

page_idx can not be negative so changing it from int to u64 and its
related changes in various files.

This also fixes MISRA 10.4 violations in these files.

Jira NVGPU-992

Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801632
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
index f78df0b5..d7399403 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
@@ -366,13 +366,13 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c,
         g->ops.fifo.add_sema_cmd(g, s, va, cmd, off, acquire, wfi);
 
         if (acquire) {
-                gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3d"
+                gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3llu"
                                      "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u",
                                      ch, nvgpu_semaphore_get_value(s),
                                      s->location.pool->page_idx, va, cmd->gva,
                                      cmd->mem->gpu_va, ob);
         } else {
-                gpu_sema_verbose_dbg(g, "(R) c=%d INCR %u (%u) pool=%-3d"
+                gpu_sema_verbose_dbg(g, "(R) c=%d INCR %u (%u) pool=%-3llu"
                                      "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u",
                                      ch, nvgpu_semaphore_get_value(s),
                                      nvgpu_semaphore_read(s),