gpu: nvgpu: falcon queue support

-Renamed "struct pmu_queue" to "struct
 nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
 moved to new file falcon_queue.c
-Created ops for queue functions in struct
 nvgpu_falcon_queue to support different queue
 types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
 to add engine specific queue functionality & assigned
 correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
 struct pmu_queue & calling queue functions using
 nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
 "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
 & also for functions gk20a_pmu_queue_head()/
 gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
 for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c

Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 15 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index 9ca7d91b..c55b90b6 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -649,12 +649,15 @@ void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn)
 
 static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
 {
+        struct gk20a *g = flcn->g;
         struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
                         &flcn->flcn_engine_dep_ops;
 
         switch (flcn->flcn_id) {
         case FALCON_ID_PMU:
                 flcn_eng_dep_ops->reset_eng = nvgpu_pmu_reset;
+                flcn_eng_dep_ops->queue_head = g->ops.pmu.pmu_queue_head;
+                flcn_eng_dep_ops->queue_tail = g->ops.pmu.pmu_queue_tail;
                 break;
         default:
                 /* NULL assignment make sure
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index cfc9128d..6d19d8a3 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -771,7 +771,7 @@ struct gpu_ops {
                 u32 (*pmu_allocation_get_fb_size)(
                                 struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
                 void (*get_pmu_init_msg_pmu_queue_params)(
-                                struct pmu_queue *queue, u32 id,
+                                struct nvgpu_falcon_queue *queue, u32 id,
                                 void *pmu_init_msg);
                 void *(*get_pmu_msg_pmu_init_msg_ptr)(
                                 struct pmu_init_msg *init);
@@ -1003,10 +1003,10 @@ struct gpu_ops {
                 u32 (*pmu_get_queue_head_size)(void);
                 u32 (*pmu_get_queue_tail_size)(void);
                 u32 (*pmu_get_queue_tail)(u32 i);
-                int (*pmu_queue_head)(struct nvgpu_pmu *pmu,
-                        struct pmu_queue *queue, u32 *head, bool set);
-                int (*pmu_queue_tail)(struct nvgpu_pmu *pmu,
-                        struct pmu_queue *queue, u32 *tail, bool set);
+                int (*pmu_queue_head)(struct gk20a *g,
+                        struct nvgpu_falcon_queue *queue, u32 *head, bool set);
+                int (*pmu_queue_tail)(struct gk20a *g,
+                        struct nvgpu_falcon_queue *queue, u32 *tail, bool set);
                 void (*pmu_msgq_tail)(struct nvgpu_pmu *pmu,
                         u32 *tail, bool set);
                 u32 (*pmu_mutex_size)(void);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 11db5b23..bf4673bf 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -377,10 +377,9 @@ int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token)
         return 0;
 }
 
-int gk20a_pmu_queue_head(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
+int gk20a_pmu_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue,
                         u32 *head, bool set)
 {
-        struct gk20a *g = gk20a_from_pmu(pmu);
         u32 queue_head_size = 0;
 
         if (g->ops.pmu.pmu_get_queue_head_size)
@@ -414,10 +413,9 @@ int gk20a_pmu_queue_head(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
         return 0;
 }
 
-int gk20a_pmu_queue_tail(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
+int gk20a_pmu_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue,
                         u32 *tail, bool set)
 {
-        struct gk20a *g = gk20a_from_pmu(pmu);
         u32 queue_tail_size = 0;
 
         if (g->ops.pmu.pmu_get_queue_tail_size)
@@ -692,7 +690,7 @@ bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu)
 void gk20a_pmu_isr(struct gk20a *g)
 {
         struct nvgpu_pmu *pmu = &g->pmu;
-        struct pmu_queue *queue;
+        struct nvgpu_falcon_queue *queue;
         u32 intr, mask;
         bool recheck = false;
 
@@ -749,9 +747,10 @@ void gk20a_pmu_isr(struct gk20a *g)
 
         if (recheck) {
                 queue = &pmu->queue[PMU_MESSAGE_QUEUE];
-                if (!nvgpu_pmu_queue_is_empty(pmu, queue))
+                if (!nvgpu_flcn_queue_is_empty(pmu->flcn, queue)) {
                         gk20a_writel(g, pwr_falcon_irqsset_r(),
                                 pwr_falcon_irqsset_swgen0_set_f());
+                }
         }
 
         nvgpu_mutex_release(&pmu->isr_mutex);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 27d27007..d9c53c28 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -49,9 +49,9 @@ void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id);
 int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
 int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
 
-int gk20a_pmu_queue_head(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
+int gk20a_pmu_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue,
                         u32 *head, bool set);
-int gk20a_pmu_queue_tail(struct nvgpu_pmu *pmu, struct pmu_queue *queue,
+int gk20a_pmu_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue,
                         u32 *tail, bool set);
 void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);