diff options
author | Philip Elcan <pelcan@nvidia.com> | 2018-08-23 14:45:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:47:25 -0400 |
commit | 2d0149c9abd74fd6bb59e076cfd46f49097e5662 (patch) | |
tree | 3d14929f7721440b777abfc150a35abbb1b03f36 /drivers/gpu/nvgpu/gk20a | |
parent | 74639b444251d7adc222400625eb59a3d53d0c0a (diff) |
gpu: nvgpu: resolve MISRA 10.3 violations
MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.
This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.
JIRA NVGPU-647
Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 5a888303..e51d768b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1124,20 +1124,20 @@ struct gpu_ops { | |||
1124 | u64 num_ops); | 1124 | u64 num_ops); |
1125 | const struct regop_offset_range* ( | 1125 | const struct regop_offset_range* ( |
1126 | *get_global_whitelist_ranges)(void); | 1126 | *get_global_whitelist_ranges)(void); |
1127 | int (*get_global_whitelist_ranges_count)(void); | 1127 | u64 (*get_global_whitelist_ranges_count)(void); |
1128 | const struct regop_offset_range* ( | 1128 | const struct regop_offset_range* ( |
1129 | *get_context_whitelist_ranges)(void); | 1129 | *get_context_whitelist_ranges)(void); |
1130 | int (*get_context_whitelist_ranges_count)(void); | 1130 | u64 (*get_context_whitelist_ranges_count)(void); |
1131 | const u32* (*get_runcontrol_whitelist)(void); | 1131 | const u32* (*get_runcontrol_whitelist)(void); |
1132 | int (*get_runcontrol_whitelist_count)(void); | 1132 | u64 (*get_runcontrol_whitelist_count)(void); |
1133 | const struct regop_offset_range* ( | 1133 | const struct regop_offset_range* ( |
1134 | *get_runcontrol_whitelist_ranges)(void); | 1134 | *get_runcontrol_whitelist_ranges)(void); |
1135 | int (*get_runcontrol_whitelist_ranges_count)(void); | 1135 | u64 (*get_runcontrol_whitelist_ranges_count)(void); |
1136 | const u32* (*get_qctl_whitelist)(void); | 1136 | const u32* (*get_qctl_whitelist)(void); |
1137 | int (*get_qctl_whitelist_count)(void); | 1137 | u64 (*get_qctl_whitelist_count)(void); |
1138 | const struct regop_offset_range* ( | 1138 | const struct regop_offset_range* ( |
1139 | *get_qctl_whitelist_ranges)(void); | 1139 | *get_qctl_whitelist_ranges)(void); |
1140 | int (*get_qctl_whitelist_ranges_count)(void); | 1140 | u64 (*get_qctl_whitelist_ranges_count)(void); |
1141 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); | 1141 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); |
1142 | } regops; | 1142 | } regops; |
1143 | struct { | 1143 | struct { |