diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-05-12 13:32:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-17 13:24:25 -0400 |
commit | 2c822a63885ec79ac2d860e13438c6154e23e5d0 (patch) | |
tree | eab486eb38d2d74b211ad94e4c1d28368922a23c /drivers/gpu/nvgpu/gk20a | |
parent | 39a9e251da0fb4da8512593d3ce4f6eba47d5e0c (diff) |
gpu: nvgpu: Remove uses of platform->can_elpg
Remove newly introduced uses of gk20a_platform->can_elpg. Rename the
field to can_elpg_init and replace all uses with gk20a->can_elpg.
Change-Id: Id6e84d4c16159b5da80c583a8a94a9c5cc2423ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1480955
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 5 |
5 files changed, 9 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index f212e55b..d6043df2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1206,7 +1206,6 @@ static inline void get_exception_mmu_fault_info( | |||
1206 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | 1206 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) |
1207 | { | 1207 | { |
1208 | struct fifo_gk20a *f = NULL; | 1208 | struct fifo_gk20a *f = NULL; |
1209 | struct gk20a_platform *platform; | ||
1210 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1209 | u32 engine_enum = ENGINE_INVAL_GK20A; |
1211 | u32 inst_id = 0; | 1210 | u32 inst_id = 0; |
1212 | struct fifo_engine_info_gk20a *engine_info; | 1211 | struct fifo_engine_info_gk20a *engine_info; |
@@ -1217,7 +1216,6 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1217 | return; | 1216 | return; |
1218 | 1217 | ||
1219 | f = &g->fifo; | 1218 | f = &g->fifo; |
1220 | platform = dev_get_drvdata(g->dev); | ||
1221 | 1219 | ||
1222 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); | 1220 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); |
1223 | 1221 | ||
@@ -1230,7 +1228,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1230 | nvgpu_err(g, "unsupported engine_id %d", engine_id); | 1228 | nvgpu_err(g, "unsupported engine_id %d", engine_id); |
1231 | 1229 | ||
1232 | if (engine_enum == ENGINE_GR_GK20A) { | 1230 | if (engine_enum == ENGINE_GR_GK20A) { |
1233 | if (g->support_pmu && platform->can_elpg) | 1231 | if (g->support_pmu && g->can_elpg) |
1234 | gk20a_pmu_disable_elpg(g); | 1232 | gk20a_pmu_disable_elpg(g); |
1235 | /* resetting engine will alter read/write index. | 1233 | /* resetting engine will alter read/write index. |
1236 | * need to flush circular buffer before re-enabling FECS. | 1234 | * need to flush circular buffer before re-enabling FECS. |
@@ -1243,7 +1241,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1243 | /* resetting engine using mc_enable_r() is not | 1241 | /* resetting engine using mc_enable_r() is not |
1244 | enough, we do full init sequence */ | 1242 | enough, we do full init sequence */ |
1245 | gk20a_gr_reset(g); | 1243 | gk20a_gr_reset(g); |
1246 | if (g->support_pmu && platform->can_elpg) | 1244 | if (g->support_pmu && g->can_elpg) |
1247 | gk20a_pmu_enable_elpg(g); | 1245 | gk20a_pmu_enable_elpg(g); |
1248 | } | 1246 | } |
1249 | if ((engine_enum == ENGINE_GRCE_GK20A) || | 1247 | if ((engine_enum == ENGINE_GRCE_GK20A) || |
@@ -1468,7 +1466,6 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1468 | bool id_is_tsg) | 1466 | bool id_is_tsg) |
1469 | { | 1467 | { |
1470 | bool fake_fault; | 1468 | bool fake_fault; |
1471 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1472 | unsigned long fault_id; | 1469 | unsigned long fault_id; |
1473 | unsigned long engine_mmu_fault_id; | 1470 | unsigned long engine_mmu_fault_id; |
1474 | bool verbose = true; | 1471 | bool verbose = true; |
@@ -1479,7 +1476,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1479 | g->fifo.deferred_reset_pending = false; | 1476 | g->fifo.deferred_reset_pending = false; |
1480 | 1477 | ||
1481 | /* Disable power management */ | 1478 | /* Disable power management */ |
1482 | if (g->support_pmu && platform->can_elpg) | 1479 | if (g->support_pmu && g->can_elpg) |
1483 | gk20a_pmu_disable_elpg(g); | 1480 | gk20a_pmu_disable_elpg(g); |
1484 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) | 1481 | if (g->ops.clock_gating.slcg_gr_load_gating_prod) |
1485 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, | 1482 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, |
@@ -1678,7 +1675,7 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1678 | gr_gpfifo_ctl_semaphore_access_enabled_f()); | 1675 | gr_gpfifo_ctl_semaphore_access_enabled_f()); |
1679 | 1676 | ||
1680 | /* It is safe to enable ELPG again. */ | 1677 | /* It is safe to enable ELPG again. */ |
1681 | if (g->support_pmu && platform->can_elpg) | 1678 | if (g->support_pmu && g->can_elpg) |
1682 | gk20a_pmu_enable_elpg(g); | 1679 | gk20a_pmu_enable_elpg(g); |
1683 | 1680 | ||
1684 | return verbose; | 1681 | return verbose; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 25636bbd..8217a8bf 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3126,7 +3126,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3126 | struct nvgpu_alloc_obj_ctx_args *args) | 3126 | struct nvgpu_alloc_obj_ctx_args *args) |
3127 | { | 3127 | { |
3128 | struct gk20a *g = c->g; | 3128 | struct gk20a *g = c->g; |
3129 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
3130 | struct fifo_gk20a *f = &g->fifo; | 3129 | struct fifo_gk20a *f = &g->fifo; |
3131 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 3130 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
3132 | struct tsg_gk20a *tsg = NULL; | 3131 | struct tsg_gk20a *tsg = NULL; |
@@ -3281,7 +3280,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3281 | 3280 | ||
3282 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; | 3281 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; |
3283 | 3282 | ||
3284 | if (g->support_pmu && platform->can_elpg) | 3283 | if (g->support_pmu && g->can_elpg) |
3285 | gk20a_pmu_enable_elpg(g); | 3284 | gk20a_pmu_enable_elpg(g); |
3286 | } | 3285 | } |
3287 | 3286 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index 2cbc1056..5dc55b18 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h | |||
@@ -42,7 +42,7 @@ struct gk20a_platform { | |||
42 | bool can_railgate_init; | 42 | bool can_railgate_init; |
43 | 43 | ||
44 | /* Should be populated at probe. */ | 44 | /* Should be populated at probe. */ |
45 | bool can_elpg; | 45 | bool can_elpg_init; |
46 | 46 | ||
47 | /* Should be populated at probe. */ | 47 | /* Should be populated at probe. */ |
48 | bool has_syncpoints; | 48 | bool has_syncpoints; |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c index e38ad506..049d394e 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/gk20a/platform_vgpu_tegra.c | |||
@@ -53,7 +53,7 @@ struct gk20a_platform vgpu_tegra_platform = { | |||
53 | 53 | ||
54 | /* power management configuration */ | 54 | /* power management configuration */ |
55 | .can_railgate_init = false, | 55 | .can_railgate_init = false, |
56 | .can_elpg = false, | 56 | .can_elpg_init = false, |
57 | .enable_slcg = false, | 57 | .enable_slcg = false, |
58 | .enable_blcg = false, | 58 | .enable_blcg = false, |
59 | .enable_elcg = false, | 59 | .enable_elcg = false, |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index af22b13f..fa0911ab 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -4936,7 +4936,6 @@ clean_up: | |||
4936 | int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | 4936 | int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) |
4937 | { | 4937 | { |
4938 | u32 status = 0; | 4938 | u32 status = 0; |
4939 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
4940 | 4939 | ||
4941 | if (enable_pg == true) { | 4940 | if (enable_pg == true) { |
4942 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 4941 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -4946,7 +4945,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4946 | if (g->ops.pmu.pmu_lpwr_enable_pg) | 4945 | if (g->ops.pmu.pmu_lpwr_enable_pg) |
4947 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, | 4946 | status = g->ops.pmu.pmu_lpwr_enable_pg(g, |
4948 | true); | 4947 | true); |
4949 | } else if (g->support_pmu && platform->can_elpg) | 4948 | } else if (g->support_pmu && g->can_elpg) |
4950 | status = gk20a_pmu_enable_elpg(g); | 4949 | status = gk20a_pmu_enable_elpg(g); |
4951 | } else if (enable_pg == false) { | 4950 | } else if (enable_pg == false) { |
4952 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 4951 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
@@ -4956,7 +4955,7 @@ int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg) | |||
4956 | if (g->ops.pmu.pmu_lpwr_disable_pg) | 4955 | if (g->ops.pmu.pmu_lpwr_disable_pg) |
4957 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, | 4956 | status = g->ops.pmu.pmu_lpwr_disable_pg(g, |
4958 | true); | 4957 | true); |
4959 | } else if (g->support_pmu && platform->can_elpg) | 4958 | } else if (g->support_pmu && g->can_elpg) |
4960 | status = gk20a_pmu_disable_elpg(g); | 4959 | status = gk20a_pmu_disable_elpg(g); |
4961 | } | 4960 | } |
4962 | 4961 | ||