diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-06-01 04:02:09 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-06 14:04:57 -0400 |
commit | 26487b82df0c6604cc40fd6480f7ad7ed4e3efb0 (patch) | |
tree | 84a2180a0b6d964384e1ad6205f998338df74e9e /drivers/gpu/nvgpu/gk20a | |
parent | 9902a49b0bc43ceb64076bce78fe8189ccd24e17 (diff) |
gpu: nvgpu: move clk_gm20b debugfs to Linux module
Move debugfs code from clk_gm20b.c to file in Linux module
common/linux/debug_clk.c
This file will be compiled only if CONFIG_DEBUG_FS is set
Define below new HAL APIs for various clock operations
which can be accessed from debug file
init_debugfs()
get_voltage()
get_gpcclk_clock_counter()
pll_reg_write()
get_pll_debug_data()
Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so
that these can be accessed from debug_clk.c
Add new structure nvgpu_clk_pll_debug_data so that
all required register values for debugging can be
made available in debug_clk.c
Add new API gm20b_get_gpc_pll_parms() so that statically
defined variable can be accessed in debug_clk.c too
Remove global variable dvfs_safe_max_freq and add
it to struct clk_gk20a so that it can accessed
from both clk_gm20b.c and debug_clk.c
Jira NVGPU-62
Change-Id: I3ae70b40235e78141a686686930e1f178ad59453
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1488903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index 65f82263..e8c14e43 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -97,6 +97,7 @@ struct clk_gk20a { | |||
97 | bool clk_hw_on; | 97 | bool clk_hw_on; |
98 | bool debugfs_set; | 98 | bool debugfs_set; |
99 | int pll_poweron_uv; | 99 | int pll_poweron_uv; |
100 | unsigned long dvfs_safe_max_freq; | ||
100 | }; | 101 | }; |
101 | 102 | ||
102 | #if defined(CONFIG_COMMON_CLK) | 103 | #if defined(CONFIG_COMMON_CLK) |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 37e2e185..4fc626e8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -31,6 +31,7 @@ struct nvgpu_mem_alloc_tracker; | |||
31 | struct dbg_profiler_object_data; | 31 | struct dbg_profiler_object_data; |
32 | struct ecc_gk20a; | 32 | struct ecc_gk20a; |
33 | struct gk20a_debug_output; | 33 | struct gk20a_debug_output; |
34 | struct nvgpu_clk_pll_debug_data; | ||
34 | 35 | ||
35 | #include <linux/sched.h> | 36 | #include <linux/sched.h> |
36 | #include <nvgpu/lock.h> | 37 | #include <nvgpu/lock.h> |
@@ -777,6 +778,7 @@ struct gpu_ops { | |||
777 | void (*set_irqmask)(struct gk20a *g); | 778 | void (*set_irqmask)(struct gk20a *g); |
778 | } pmu; | 779 | } pmu; |
779 | struct { | 780 | struct { |
781 | int (*init_debugfs)(struct gk20a *g); | ||
780 | void (*disable_slowboot)(struct gk20a *g); | 782 | void (*disable_slowboot)(struct gk20a *g); |
781 | int (*init_clk_support)(struct gk20a *g); | 783 | int (*init_clk_support)(struct gk20a *g); |
782 | int (*suspend_clk_support)(struct gk20a *g); | 784 | int (*suspend_clk_support)(struct gk20a *g); |
@@ -791,6 +793,11 @@ struct gpu_ops { | |||
791 | unsigned long (*get_maxrate)(struct clk_gk20a *clk); | 793 | unsigned long (*get_maxrate)(struct clk_gk20a *clk); |
792 | int (*prepare_enable)(struct clk_gk20a *clk); | 794 | int (*prepare_enable)(struct clk_gk20a *clk); |
793 | void (*disable_unprepare)(struct clk_gk20a *clk); | 795 | void (*disable_unprepare)(struct clk_gk20a *clk); |
796 | int (*get_voltage)(struct clk_gk20a *clk, u64 *val); | ||
797 | int (*get_gpcclk_clock_counter)(struct clk_gk20a *clk, u64 *val); | ||
798 | int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val); | ||
799 | int (*get_pll_debug_data)(struct gk20a *g, | ||
800 | struct nvgpu_clk_pll_debug_data *d); | ||
794 | } clk; | 801 | } clk; |
795 | struct { | 802 | struct { |
796 | u32 (*get_arbiter_clk_domains)(struct gk20a *g); | 803 | u32 (*get_arbiter_clk_domains)(struct gk20a *g); |