diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2015-09-14 12:51:24 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-15 17:35:33 -0400 |
commit | 2359f247d18fbde3220e463543193ab06f75fe81 (patch) | |
tree | 535b99801b3e78ba040963e23cda70d30b9e8c4a /drivers/gpu/nvgpu/gk20a | |
parent | 1b2faa54260def17037ac6f04e3f32361c5a8f92 (diff) |
gpu: nvgpu: HAL to write DMATRFBASE
Bug 200137618
Change-Id: I18b980876e93c3f7287082701e1d2b998cd33114
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798777
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 10 |
2 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d48b94aa..dd7a7ad4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -390,6 +390,7 @@ struct gpu_ops { | |||
390 | int (*pmu_setup_elpg)(struct gk20a *g); | 390 | int (*pmu_setup_elpg)(struct gk20a *g); |
391 | int (*init_wpr_region)(struct gk20a *g); | 391 | int (*init_wpr_region)(struct gk20a *g); |
392 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); | 392 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); |
393 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); | ||
393 | u32 lspmuwprinitdone; | 394 | u32 lspmuwprinitdone; |
394 | u32 lsfloadedfalconid; | 395 | u32 lsfloadedfalconid; |
395 | bool fecsbootstrapdone; | 396 | bool fecsbootstrapdone; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 18404ec0..110f3c5a 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1763,8 +1763,8 @@ static int pmu_bootstrap(struct pmu_gk20a *pmu) | |||
1763 | gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x1); | 1763 | gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x1); |
1764 | gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_args); | 1764 | gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_args); |
1765 | 1765 | ||
1766 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), | 1766 | g->ops.pmu.write_dmatrfbase(g, |
1767 | addr_load - (desc->bootloader_imem_offset >> 8)); | 1767 | addr_load - (desc->bootloader_imem_offset >> 8)); |
1768 | 1768 | ||
1769 | blocks = ((desc->bootloader_size + 0xFF) & ~0xFF) >> 8; | 1769 | blocks = ((desc->bootloader_size + 0xFF) & ~0xFF) >> 8; |
1770 | 1770 | ||
@@ -2643,6 +2643,11 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
2643 | } | 2643 | } |
2644 | } | 2644 | } |
2645 | 2645 | ||
2646 | static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | ||
2647 | { | ||
2648 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | ||
2649 | } | ||
2650 | |||
2646 | void gk20a_init_pmu_ops(struct gpu_ops *gops) | 2651 | void gk20a_init_pmu_ops(struct gpu_ops *gops) |
2647 | { | 2652 | { |
2648 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; | 2653 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; |
@@ -2651,6 +2656,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2651 | gops->pmu.pmu_setup_elpg = NULL; | 2656 | gops->pmu.pmu_setup_elpg = NULL; |
2652 | gops->pmu.init_wpr_region = NULL; | 2657 | gops->pmu.init_wpr_region = NULL; |
2653 | gops->pmu.load_lsfalcon_ucode = NULL; | 2658 | gops->pmu.load_lsfalcon_ucode = NULL; |
2659 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; | ||
2654 | } | 2660 | } |
2655 | 2661 | ||
2656 | int gk20a_init_pmu_support(struct gk20a *g) | 2662 | int gk20a_init_pmu_support(struct gk20a *g) |