diff options
author | Amulya <Amurthyreddy@nvidia.com> | 2018-08-06 01:07:32 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-14 00:51:09 -0400 |
commit | 2328d305b7c9437aa467922086b9fcfc0a4169ba (patch) | |
tree | 6d37f0f7bda427c296cfb06021715a2e01581f0c /drivers/gpu/nvgpu/gk20a | |
parent | e62785190f74cfbf9003a190a768e9077373bf6f (diff) |
gpu: nvgpu: MISRA 10.4 enum fixes
MISRA rule-10.4 only allows arithmetic conversions on operands of the
same essential type category.
Fix violations where an arithmetic conversion is performed on enum and
non-enum types.
JIRA NVGPU-993
Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792852
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 |
4 files changed, 17 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 98fdb8c2..92f88333 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -139,7 +139,8 @@ static bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn) | |||
139 | return status; | 139 | return status; |
140 | } | 140 | } |
141 | 141 | ||
142 | static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, u32 mem_type) | 142 | static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, |
143 | enum flcn_mem_type mem_type) | ||
143 | { | 144 | { |
144 | struct gk20a *g = flcn->g; | 145 | struct gk20a *g = flcn->g; |
145 | u32 mem_size = 0; | 146 | u32 mem_size = 0; |
@@ -157,7 +158,7 @@ static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, u32 mem_type) | |||
157 | } | 158 | } |
158 | 159 | ||
159 | static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn, | 160 | static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn, |
160 | u32 offset, u32 size, u32 mem_type) | 161 | u32 offset, u32 size, enum flcn_mem_type mem_type) |
161 | { | 162 | { |
162 | struct gk20a *g = flcn->g; | 163 | struct gk20a *g = flcn->g; |
163 | u32 mem_size = 0; | 164 | u32 mem_size = 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c29c03f0..204fd371 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -250,7 +250,7 @@ struct gpu_ops { | |||
250 | int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, | 250 | int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, |
251 | struct gr_zcull_info *zcull_params); | 251 | struct gr_zcull_info *zcull_params); |
252 | int (*decode_egpc_addr)(struct gk20a *g, | 252 | int (*decode_egpc_addr)(struct gk20a *g, |
253 | u32 addr, int *addr_type, | 253 | u32 addr, enum ctxsw_addr_type *addr_type, |
254 | u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); | 254 | u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); |
255 | void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr, | 255 | void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr, |
256 | u32 gpc, u32 tpc, u32 broadcast_flags, | 256 | u32 gpc, u32 tpc, u32 broadcast_flags, |
@@ -473,7 +473,7 @@ struct gpu_ops { | |||
473 | u32 *count, u32 *offset, | 473 | u32 *count, u32 *offset, |
474 | u32 max_cnt, u32 base, u32 mask); | 474 | u32 max_cnt, u32 base, u32 mask); |
475 | int (*decode_priv_addr)(struct gk20a *g, u32 addr, | 475 | int (*decode_priv_addr)(struct gk20a *g, u32 addr, |
476 | int *addr_type, | 476 | enum ctxsw_addr_type *addr_type, |
477 | u32 *gpc_num, u32 *tpc_num, | 477 | u32 *gpc_num, u32 *tpc_num, |
478 | u32 *ppc_num, u32 *be_num, | 478 | u32 *ppc_num, u32 *be_num, |
479 | u32 *broadcast_flags); | 479 | u32 *broadcast_flags); |
@@ -495,8 +495,9 @@ struct gpu_ops { | |||
495 | struct channel_gk20a *c, bool patch); | 495 | struct channel_gk20a *c, bool patch); |
496 | u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc); | 496 | u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc); |
497 | int (*get_offset_in_gpccs_segment)(struct gk20a *g, | 497 | int (*get_offset_in_gpccs_segment)(struct gk20a *g, |
498 | int addr_type, u32 num_tpcs, u32 num_ppcs, | 498 | enum ctxsw_addr_type addr_type, u32 num_tpcs, |
499 | u32 reg_list_ppc_count, u32 *__offset_in_segment); | 499 | u32 num_ppcs, u32 reg_list_ppc_count, |
500 | u32 *__offset_in_segment); | ||
500 | } gr; | 501 | } gr; |
501 | struct { | 502 | struct { |
502 | void (*init_hw)(struct gk20a *g); | 503 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index bedd39eb..5539b801 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6274,7 +6274,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g, | |||
6274 | 6274 | ||
6275 | /* This function will decode a priv address and return the partition type and numbers. */ | 6275 | /* This function will decode a priv address and return the partition type and numbers. */ |
6276 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | 6276 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, |
6277 | int *addr_type, /* enum ctxsw_addr_type */ | 6277 | enum ctxsw_addr_type *addr_type, |
6278 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | 6278 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, |
6279 | u32 *broadcast_flags) | 6279 | u32 *broadcast_flags) |
6280 | { | 6280 | { |
@@ -6391,7 +6391,7 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g, | |||
6391 | u32 *priv_addr_table, | 6391 | u32 *priv_addr_table, |
6392 | u32 *num_registers) | 6392 | u32 *num_registers) |
6393 | { | 6393 | { |
6394 | int addr_type; /*enum ctxsw_addr_type */ | 6394 | enum ctxsw_addr_type addr_type; |
6395 | u32 gpc_num, tpc_num, ppc_num, be_num; | 6395 | u32 gpc_num, tpc_num, ppc_num, be_num; |
6396 | u32 priv_addr, gpc_addr; | 6396 | u32 priv_addr, gpc_addr; |
6397 | u32 broadcast_flags; | 6397 | u32 broadcast_flags; |
@@ -7036,7 +7036,7 @@ static int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g, | |||
7036 | 7036 | ||
7037 | static int | 7037 | static int |
7038 | gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g, | 7038 | gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g, |
7039 | int addr_type,/* enum ctxsw_addr_type */ | 7039 | enum ctxsw_addr_type addr_type, |
7040 | u32 pri_addr, | 7040 | u32 pri_addr, |
7041 | u32 gpc_num, u32 num_tpcs, | 7041 | u32 gpc_num, u32 num_tpcs, |
7042 | u32 num_ppcs, u32 ppc_mask, | 7042 | u32 num_ppcs, u32 ppc_mask, |
@@ -7214,7 +7214,7 @@ static int gr_gk20a_determine_ppc_configuration(struct gk20a *g, | |||
7214 | } | 7214 | } |
7215 | 7215 | ||
7216 | int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, | 7216 | int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, |
7217 | int addr_type, | 7217 | enum ctxsw_addr_type addr_type, |
7218 | u32 num_tpcs, | 7218 | u32 num_tpcs, |
7219 | u32 num_ppcs, | 7219 | u32 num_ppcs, |
7220 | u32 reg_list_ppc_count, | 7220 | u32 reg_list_ppc_count, |
@@ -7289,7 +7289,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g, | |||
7289 | { | 7289 | { |
7290 | u32 i, data32; | 7290 | u32 i, data32; |
7291 | int err; | 7291 | int err; |
7292 | int addr_type; /*enum ctxsw_addr_type */ | 7292 | enum ctxsw_addr_type addr_type; |
7293 | u32 broadcast_flags; | 7293 | u32 broadcast_flags; |
7294 | u32 gpc_num, tpc_num, ppc_num, be_num; | 7294 | u32 gpc_num, tpc_num, ppc_num, be_num; |
7295 | u32 num_gpcs, num_tpcs, num_ppcs; | 7295 | u32 num_gpcs, num_tpcs, num_ppcs; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 804e0e25..2b31b6b6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -70,6 +70,8 @@ struct tsg_gk20a; | |||
70 | struct channel_gk20a; | 70 | struct channel_gk20a; |
71 | struct nvgpu_warpstate; | 71 | struct nvgpu_warpstate; |
72 | 72 | ||
73 | enum ctxsw_addr_type; | ||
74 | |||
73 | enum /* global_ctx_buffer */ { | 75 | enum /* global_ctx_buffer */ { |
74 | CIRCULAR = 0, | 76 | CIRCULAR = 0, |
75 | PAGEPOOL = 1, | 77 | PAGEPOOL = 1, |
@@ -842,7 +844,7 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, | |||
842 | u32 *count, u32 *offset, | 844 | u32 *count, u32 *offset, |
843 | u32 max_cnt, u32 base, u32 mask); | 845 | u32 max_cnt, u32 base, u32 mask); |
844 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | 846 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, |
845 | int *addr_type, | 847 | enum ctxsw_addr_type *addr_type, |
846 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | 848 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, |
847 | u32 *broadcast_flags); | 849 | u32 *broadcast_flags); |
848 | int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr, | 850 | int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr, |
@@ -856,7 +858,7 @@ void gr_gk20a_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, | |||
856 | u32 num_fbpas, | 858 | u32 num_fbpas, |
857 | u32 *priv_addr_table, u32 *t); | 859 | u32 *priv_addr_table, u32 *t); |
858 | int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, | 860 | int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, |
859 | int addr_type, u32 num_tpcs, u32 num_ppcs, | 861 | enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, |
860 | u32 reg_list_ppc_count, u32 *__offset_in_segment); | 862 | u32 reg_list_ppc_count, u32 *__offset_in_segment); |
861 | 863 | ||
862 | void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, | 864 | void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, |