gpu: nvgpu: Remove mm.get_iova_addr

Remove the mm.get_iova_addr() HAL and replace it with a new HAL
called mm.gpu_phys_addr(). This new HAL provides the real phys
address that should be passed to the GPU from a physical address
obtained from a scatter list. It also provides a mechanism by
which the HAL code can add extra bits to a GPU physical address
based on the attributes passed in. This is necessary during GMMU
page table programming.

Also remove the flags argument from the various address functions.
This flag was used for adding an IO coherence bit to the GPU
physical address which is not supported.

JIRA NVGPU-30

Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530864
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 17 insertions, 59 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
index c5f9c1fd..79f469cd 100644
--- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
@@ -44,8 +44,7 @@ void fb_gk20a_reset(struct gk20a *g)
 
 void gk20a_fb_init_hw(struct gk20a *g)
 {
-        u32 addr = g->ops.mm.get_iova_addr(g,
-                        g->mm.sysmem_flush.priv.sgt->sgl, 0) >> 8;
+        u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
 
         gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
 }
@@ -67,7 +66,7 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
         if (!g->power_on)
                 return;
 
-        addr_lo = u64_lo32(nvgpu_mem_get_base_addr(g, pdb, 0) >> 12);
+        addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12);
 
         nvgpu_mutex_acquire(&g->mm.tlb_lock);
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 347ee7dd..c0fef59d 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -891,8 +891,8 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
 
         for (chid = 0; chid < f->num_channels; chid++) {
                 f->channel[chid].userd_iova =
-                        g->ops.mm.get_iova_addr(g, f->userd.priv.sgt->sgl, 0)
-                        + chid * f->userd_entry_size;
+                        nvgpu_mem_get_addr(g, &f->userd) +
+                        chid * f->userd_entry_size;
                 f->channel[chid].userd_gpu_va =
                         f->userd.gpu_va + chid * f->userd_entry_size;
                 gk20a_init_channel_support(g, chid);
@@ -3106,8 +3106,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
         old_buf = runlist->cur_buffer;
         new_buf = !runlist->cur_buffer;
 
-        runlist_iova = g->ops.mm.get_iova_addr(
-                        g, runlist->mem[new_buf].priv.sgt->sgl, 0);
+        runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]);
 
         gk20a_dbg_info("runlist_id : %d, switch to new buffer 0x%16llx",
                 runlist_id, (u64)runlist_iova);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 4517f6e0..7b998204 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -730,8 +730,6 @@ struct gpu_ops {
                                 struct vm_gk20a *vm);
                 u64 (*gpu_phys_addr)(struct gk20a *g,
                                      struct nvgpu_gmmu_attrs *attrs, u64 phys);
-                u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl,
-                                         u32 flags);
                 size_t (*get_vidmem_size)(struct gk20a *g);
                 void (*init_inst_block)(struct nvgpu_mem *inst_block,
                                 struct vm_gk20a *vm, u32 big_page_size);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 1fc57a56..497e7ee2 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4443,7 +4443,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
         gk20a_dbg_fn("");
 
         /* init mmu debug buffer */
-        addr = g->ops.mm.get_iova_addr(g, gr->mmu_wr_mem.priv.sgt->sgl, 0);
+        addr = nvgpu_mem_get_addr(g, &gr->mmu_wr_mem);
         addr >>= fb_mmu_debug_wr_addr_alignment_v();
 
         gk20a_writel(g, fb_mmu_debug_wr_r(),
@@ -4453,7 +4453,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
                      fb_mmu_debug_wr_vol_false_f() |
                      fb_mmu_debug_wr_addr_f(addr));
 
-        addr = g->ops.mm.get_iova_addr(g, gr->mmu_rd_mem.priv.sgt->sgl, 0);
+        addr = nvgpu_mem_get_addr(g, &gr->mmu_rd_mem);
         addr >>= fb_mmu_debug_rd_addr_alignment_v();
 
         gk20a_writel(g, fb_mmu_debug_rd_r(),
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index f4395116..16fe7149 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -1383,7 +1383,7 @@ int nvgpu_vm_map_compbits(struct vm_gk20a *vm,
                 return -EINVAL;
         }
 
-        *mapping_iova = gk20a_mm_iova_addr(g, mapped_buffer->sgt->sgl, 0);
+        *mapping_iova = nvgpu_mem_get_addr_sgl(g, mapped_buffer->sgt->sgl);
         *compbits_win_gva = mapped_buffer->ctag_map_win_addr;
 
         nvgpu_mutex_release(&vm->update_gmmu_lock);
@@ -1454,30 +1454,6 @@ static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct nvgpu_mem *mem)
 }
 #endif
 
-/*
- * If mem is in VIDMEM, return base address in vidmem
- * else return IOVA address for SYSMEM
- */
-u64 nvgpu_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem,
-                            u32 flags)
-{
-        struct nvgpu_page_alloc *alloc;
-        u64 addr;
-
-        if (mem->aperture == APERTURE_VIDMEM) {
-                alloc = get_vidmem_page_alloc(mem->priv.sgt->sgl);
-
-                /* This API should not be used with > 1 chunks */
-                WARN_ON(alloc->nr_chunks != 1);
-
-                addr = alloc->base;
-        } else {
-                addr = g->ops.mm.get_iova_addr(g, mem->priv.sgt->sgl, flags);
-        }
-
-        return addr;
-}
-
 #if defined(CONFIG_GK20A_VIDMEM)
 static struct nvgpu_mem *get_pending_mem_desc(struct mm_gk20a *mm)
 {
@@ -1526,8 +1502,7 @@ dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr)
         nvgpu_mutex_acquire(&vm->update_gmmu_lock);
         buffer = __nvgpu_vm_find_mapped_buf(vm, gpu_vaddr);
         if (buffer)
-                addr = g->ops.mm.get_iova_addr(g, buffer->sgt->sgl,
-                                buffer->flags);
+                addr = nvgpu_mem_get_addr_sgl(g, buffer->sgt->sgl);
         nvgpu_mutex_release(&vm->update_gmmu_lock);
 
         return addr;
@@ -1545,21 +1520,6 @@ u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova)
         return iova;
 }
 
-u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl,
-                u32 flags)
-{
-        if (!device_is_iommuable(dev_from_gk20a(g)))
-                return sg_phys(sgl);
-
-        if (sg_dma_address(sgl) == 0)
-                return sg_phys(sgl);
-
-        if (sg_dma_address(sgl) == DMA_ERROR_CODE)
-                return 0;
-
-        return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl));
-}
-
 /* for gk20a the "video memory" apertures here are misnomers. */
 static inline u32 big_valid_pde0_bits(struct gk20a *g,
                                       struct nvgpu_gmmu_pd *pd, u64 addr)
@@ -2071,7 +2031,7 @@ u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct nvgpu_mem *inst_block)
         if (g->mm.has_physical_mode)
                 addr = gk20a_mem_phys(inst_block);
         else
-                addr = nvgpu_mem_get_base_addr(g, inst_block, 0);
+                addr = nvgpu_mem_get_addr(g, inst_block);
 
         return addr;
 }
@@ -2194,7 +2154,7 @@ static int gk20a_init_ce_vm(struct mm_gk20a *mm)
 void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
                 struct vm_gk20a *vm)
 {
-        u64 pdb_addr = nvgpu_mem_get_base_addr(g, vm->pdb.mem, 0);
+        u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
         u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
         u32 pdb_addr_hi = u64_hi32(pdb_addr);
 
@@ -2465,6 +2425,11 @@ u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g)
         return 34;
 }
 
+u64 gk20a_mm_gpu_phys_addr(struct gk20a *g, u64 phys, u32 flags)
+{
+        return phys;
+}
+
 const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
                                                       u32 big_page_size)
 {
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index c56b28bb..93baa943 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -345,11 +345,8 @@ void gk20a_mm_dump_vm(struct vm_gk20a *vm,
 
 int gk20a_mm_suspend(struct gk20a *g);
 
-u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl,
-                u32 flags);
+u64 gk20a_mm_gpu_phys_addr(struct gk20a *g, u64 phys, u32 flags);
 u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova);
-u64 nvgpu_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem,
-                            u32 flags);
 
 void gk20a_mm_ltc_isr(struct gk20a *g);